cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra20-cpufreq.c (2776B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2010 Google, Inc.
      4 *
      5 * Author:
      6 *	Colin Cross <ccross@google.com>
      7 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
      8 */
      9
     10#include <linux/bits.h>
     11#include <linux/cpu.h>
     12#include <linux/err.h>
     13#include <linux/init.h>
     14#include <linux/module.h>
     15#include <linux/of_device.h>
     16#include <linux/platform_device.h>
     17#include <linux/pm_opp.h>
     18#include <linux/types.h>
     19
     20#include <soc/tegra/common.h>
     21#include <soc/tegra/fuse.h>
     22
     23static bool cpu0_node_has_opp_v2_prop(void)
     24{
     25	struct device_node *np = of_cpu_device_node_get(0);
     26	bool ret = false;
     27
     28	if (of_get_property(np, "operating-points-v2", NULL))
     29		ret = true;
     30
     31	of_node_put(np);
     32	return ret;
     33}
     34
     35static void tegra20_cpufreq_put_supported_hw(void *opp_table)
     36{
     37	dev_pm_opp_put_supported_hw(opp_table);
     38}
     39
     40static void tegra20_cpufreq_dt_unregister(void *cpufreq_dt)
     41{
     42	platform_device_unregister(cpufreq_dt);
     43}
     44
     45static int tegra20_cpufreq_probe(struct platform_device *pdev)
     46{
     47	struct platform_device *cpufreq_dt;
     48	struct opp_table *opp_table;
     49	struct device *cpu_dev;
     50	u32 versions[2];
     51	int err;
     52
     53	if (!cpu0_node_has_opp_v2_prop()) {
     54		dev_err(&pdev->dev, "operating points not found\n");
     55		dev_err(&pdev->dev, "please update your device tree\n");
     56		return -ENODEV;
     57	}
     58
     59	if (of_machine_is_compatible("nvidia,tegra20")) {
     60		versions[0] = BIT(tegra_sku_info.cpu_process_id);
     61		versions[1] = BIT(tegra_sku_info.soc_speedo_id);
     62	} else {
     63		versions[0] = BIT(tegra_sku_info.cpu_process_id);
     64		versions[1] = BIT(tegra_sku_info.cpu_speedo_id);
     65	}
     66
     67	dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n",
     68		 versions[0], versions[1]);
     69
     70	cpu_dev = get_cpu_device(0);
     71	if (WARN_ON(!cpu_dev))
     72		return -ENODEV;
     73
     74	opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2);
     75	err = PTR_ERR_OR_ZERO(opp_table);
     76	if (err) {
     77		dev_err(&pdev->dev, "failed to set supported hw: %d\n", err);
     78		return err;
     79	}
     80
     81	err = devm_add_action_or_reset(&pdev->dev,
     82				       tegra20_cpufreq_put_supported_hw,
     83				       opp_table);
     84	if (err)
     85		return err;
     86
     87	cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
     88	err = PTR_ERR_OR_ZERO(cpufreq_dt);
     89	if (err) {
     90		dev_err(&pdev->dev,
     91			"failed to create cpufreq-dt device: %d\n", err);
     92		return err;
     93	}
     94
     95	err = devm_add_action_or_reset(&pdev->dev,
     96				       tegra20_cpufreq_dt_unregister,
     97				       cpufreq_dt);
     98	if (err)
     99		return err;
    100
    101	return 0;
    102}
    103
    104static struct platform_driver tegra20_cpufreq_driver = {
    105	.probe		= tegra20_cpufreq_probe,
    106	.driver		= {
    107		.name	= "tegra20-cpufreq",
    108	},
    109};
    110module_platform_driver(tegra20_cpufreq_driver);
    111
    112MODULE_ALIAS("platform:tegra20-cpufreq");
    113MODULE_AUTHOR("Colin Cross <ccross@android.com>");
    114MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
    115MODULE_LICENSE("GPL");