cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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psp-dev.h (2100B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * AMD Platform Security Processor (PSP) interface driver
      4 *
      5 * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
      6 *
      7 * Author: Brijesh Singh <brijesh.singh@amd.com>
      8 */
      9
     10#ifndef __PSP_DEV_H__
     11#define __PSP_DEV_H__
     12
     13#include <linux/device.h>
     14#include <linux/list.h>
     15#include <linux/bits.h>
     16#include <linux/interrupt.h>
     17
     18#include "sp-dev.h"
     19
     20#define PSP_CMDRESP_RESP		BIT(31)
     21#define PSP_CMDRESP_ERR_MASK		0xffff
     22
     23#define MAX_PSP_NAME_LEN		16
     24
     25extern struct psp_device *psp_master;
     26
     27typedef void (*psp_irq_handler_t)(int, void *, unsigned int);
     28
     29struct psp_device {
     30	struct list_head entry;
     31
     32	struct psp_vdata *vdata;
     33	char name[MAX_PSP_NAME_LEN];
     34
     35	struct device *dev;
     36	struct sp_device *sp;
     37
     38	void __iomem *io_regs;
     39
     40	psp_irq_handler_t sev_irq_handler;
     41	void *sev_irq_data;
     42
     43	psp_irq_handler_t tee_irq_handler;
     44	void *tee_irq_data;
     45
     46	void *sev_data;
     47	void *tee_data;
     48
     49	unsigned int capability;
     50};
     51
     52void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
     53			     void *data);
     54void psp_clear_sev_irq_handler(struct psp_device *psp);
     55
     56void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
     57			     void *data);
     58void psp_clear_tee_irq_handler(struct psp_device *psp);
     59
     60struct psp_device *psp_get_master_device(void);
     61
     62#define PSP_CAPABILITY_SEV			BIT(0)
     63#define PSP_CAPABILITY_TEE			BIT(1)
     64#define PSP_CAPABILITY_PSP_SECURITY_REPORTING	BIT(7)
     65
     66#define PSP_CAPABILITY_PSP_SECURITY_OFFSET	8
     67/*
     68 * The PSP doesn't directly store these bits in the capability register
     69 * but instead copies them from the results of query command.
     70 *
     71 * The offsets from the query command are below, and shifted when used.
     72 */
     73#define PSP_SECURITY_FUSED_PART			BIT(0)
     74#define PSP_SECURITY_DEBUG_LOCK_ON		BIT(2)
     75#define PSP_SECURITY_TSME_STATUS		BIT(5)
     76#define PSP_SECURITY_ANTI_ROLLBACK_STATUS	BIT(7)
     77#define PSP_SECURITY_RPMC_PRODUCTION_ENABLED	BIT(8)
     78#define PSP_SECURITY_RPMC_SPIROM_AVAILABLE	BIT(9)
     79#define PSP_SECURITY_HSP_TPM_AVAILABLE		BIT(10)
     80#define PSP_SECURITY_ROM_ARMOR_ENFORCED		BIT(11)
     81
     82#endif /* __PSP_DEV_H */