cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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otx_cptvf_algs.h (3882B)

      1/* SPDX-License-Identifier: GPL-2.0
      2 * Marvell OcteonTX CPT driver
      3 *
      4 * Copyright (C) 2019 Marvell International Ltd.
      5 *
      6 * This program is free software; you can redistribute it and/or modify
      7 * it under the terms of the GNU General Public License version 2 as
      8 * published by the Free Software Foundation.
      9 */
     10
     11#ifndef __OTX_CPT_ALGS_H
     12#define __OTX_CPT_ALGS_H
     13
     14#include <crypto/hash.h>
     15#include "otx_cpt_common.h"
     16
     17#define OTX_CPT_MAX_ENC_KEY_SIZE    32
     18#define OTX_CPT_MAX_HASH_KEY_SIZE   64
     19#define OTX_CPT_MAX_KEY_SIZE (OTX_CPT_MAX_ENC_KEY_SIZE + \
     20			      OTX_CPT_MAX_HASH_KEY_SIZE)
     21enum otx_cpt_request_type {
     22	OTX_CPT_ENC_DEC_REQ            = 0x1,
     23	OTX_CPT_AEAD_ENC_DEC_REQ       = 0x2,
     24	OTX_CPT_AEAD_ENC_DEC_NULL_REQ  = 0x3,
     25	OTX_CPT_PASSTHROUGH_REQ	       = 0x4
     26};
     27
     28enum otx_cpt_major_opcodes {
     29	OTX_CPT_MAJOR_OP_MISC = 0x01,
     30	OTX_CPT_MAJOR_OP_FC   = 0x33,
     31	OTX_CPT_MAJOR_OP_HMAC = 0x35,
     32};
     33
     34enum otx_cpt_req_type {
     35		OTX_CPT_AE_CORE_REQ,
     36		OTX_CPT_SE_CORE_REQ
     37};
     38
     39enum otx_cpt_cipher_type {
     40	OTX_CPT_CIPHER_NULL = 0x0,
     41	OTX_CPT_DES3_CBC = 0x1,
     42	OTX_CPT_DES3_ECB = 0x2,
     43	OTX_CPT_AES_CBC  = 0x3,
     44	OTX_CPT_AES_ECB  = 0x4,
     45	OTX_CPT_AES_CFB  = 0x5,
     46	OTX_CPT_AES_CTR  = 0x6,
     47	OTX_CPT_AES_GCM  = 0x7,
     48	OTX_CPT_AES_XTS  = 0x8
     49};
     50
     51enum otx_cpt_mac_type {
     52	OTX_CPT_MAC_NULL = 0x0,
     53	OTX_CPT_MD5      = 0x1,
     54	OTX_CPT_SHA1     = 0x2,
     55	OTX_CPT_SHA224   = 0x3,
     56	OTX_CPT_SHA256   = 0x4,
     57	OTX_CPT_SHA384   = 0x5,
     58	OTX_CPT_SHA512   = 0x6,
     59	OTX_CPT_GMAC     = 0x7
     60};
     61
     62enum otx_cpt_aes_key_len {
     63	OTX_CPT_AES_128_BIT = 0x1,
     64	OTX_CPT_AES_192_BIT = 0x2,
     65	OTX_CPT_AES_256_BIT = 0x3
     66};
     67
     68union otx_cpt_encr_ctrl {
     69	__be64 flags;
     70	u64 cflags;
     71	struct {
     72#if defined(__BIG_ENDIAN_BITFIELD)
     73		u64 enc_cipher:4;
     74		u64 reserved1:1;
     75		u64 aes_key:2;
     76		u64 iv_source:1;
     77		u64 mac_type:4;
     78		u64 reserved2:3;
     79		u64 auth_input_type:1;
     80		u64 mac_len:8;
     81		u64 reserved3:8;
     82		u64 encr_offset:16;
     83		u64 iv_offset:8;
     84		u64 auth_offset:8;
     85#else
     86		u64 auth_offset:8;
     87		u64 iv_offset:8;
     88		u64 encr_offset:16;
     89		u64 reserved3:8;
     90		u64 mac_len:8;
     91		u64 auth_input_type:1;
     92		u64 reserved2:3;
     93		u64 mac_type:4;
     94		u64 iv_source:1;
     95		u64 aes_key:2;
     96		u64 reserved1:1;
     97		u64 enc_cipher:4;
     98#endif
     99	} e;
    100};
    101
    102struct otx_cpt_cipher {
    103	const char *name;
    104	u8 value;
    105};
    106
    107struct otx_cpt_enc_context {
    108	union otx_cpt_encr_ctrl enc_ctrl;
    109	u8 encr_key[32];
    110	u8 encr_iv[16];
    111};
    112
    113union otx_cpt_fchmac_ctx {
    114	struct {
    115		u8 ipad[64];
    116		u8 opad[64];
    117	} e;
    118	struct {
    119		u8 hmac_calc[64]; /* HMAC calculated */
    120		u8 hmac_recv[64]; /* HMAC received */
    121	} s;
    122};
    123
    124struct otx_cpt_fc_ctx {
    125	struct otx_cpt_enc_context enc;
    126	union otx_cpt_fchmac_ctx hmac;
    127};
    128
    129struct otx_cpt_enc_ctx {
    130	u32 key_len;
    131	u8 enc_key[OTX_CPT_MAX_KEY_SIZE];
    132	u8 cipher_type;
    133	u8 key_type;
    134};
    135
    136struct otx_cpt_des3_ctx {
    137	u32 key_len;
    138	u8 des3_key[OTX_CPT_MAX_KEY_SIZE];
    139};
    140
    141union otx_cpt_offset_ctrl_word {
    142	__be64 flags;
    143	u64 cflags;
    144	struct {
    145#if defined(__BIG_ENDIAN_BITFIELD)
    146		u64 reserved:32;
    147		u64 enc_data_offset:16;
    148		u64 iv_offset:8;
    149		u64 auth_offset:8;
    150#else
    151		u64 auth_offset:8;
    152		u64 iv_offset:8;
    153		u64 enc_data_offset:16;
    154		u64 reserved:32;
    155#endif
    156	} e;
    157};
    158
    159struct otx_cpt_req_ctx {
    160	struct otx_cpt_req_info cpt_req;
    161	union otx_cpt_offset_ctrl_word ctrl_word;
    162	struct otx_cpt_fc_ctx fctx;
    163};
    164
    165struct otx_cpt_sdesc {
    166	struct shash_desc shash;
    167};
    168
    169struct otx_cpt_aead_ctx {
    170	u8 key[OTX_CPT_MAX_KEY_SIZE];
    171	struct crypto_shash *hashalg;
    172	struct otx_cpt_sdesc *sdesc;
    173	u8 *ipad;
    174	u8 *opad;
    175	u32 enc_key_len;
    176	u32 auth_key_len;
    177	u8 cipher_type;
    178	u8 mac_type;
    179	u8 key_type;
    180	u8 is_trunc_hmac;
    181};
    182int otx_cpt_crypto_init(struct pci_dev *pdev, struct module *mod,
    183			enum otx_cptpf_type pf_type,
    184			enum otx_cptvf_type engine_type,
    185			int num_queues, int num_devices);
    186void otx_cpt_crypto_exit(struct pci_dev *pdev, struct module *mod,
    187			 enum otx_cptvf_type engine_type);
    188void otx_cpt_callback(int status, void *arg, void *req);
    189
    190#endif /* __OTX_CPT_ALGS_H */