cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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adf_c3xxx_hw_data.c (4079B)

      1// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
      2/* Copyright(c) 2014 - 2021 Intel Corporation */
      3#include <adf_accel_devices.h>
      4#include <adf_common_drv.h>
      5#include <adf_gen2_hw_data.h>
      6#include <adf_gen2_pfvf.h>
      7#include "adf_c3xxx_hw_data.h"
      8#include "icp_qat_hw.h"
      9
     10/* Worker thread to service arbiter mappings */
     11static const u32 thrd_to_arb_map[ADF_C3XXX_MAX_ACCELENGINES] = {
     12	0x12222AAA, 0x11222AAA, 0x12222AAA,
     13	0x11222AAA, 0x12222AAA, 0x11222AAA
     14};
     15
     16static struct adf_hw_device_class c3xxx_class = {
     17	.name = ADF_C3XXX_DEVICE_NAME,
     18	.type = DEV_C3XXX,
     19	.instances = 0
     20};
     21
     22static u32 get_accel_mask(struct adf_hw_device_data *self)
     23{
     24	u32 straps = self->straps;
     25	u32 fuses = self->fuses;
     26	u32 accel;
     27
     28	accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
     29	accel &= ADF_C3XXX_ACCELERATORS_MASK;
     30
     31	return accel;
     32}
     33
     34static u32 get_ae_mask(struct adf_hw_device_data *self)
     35{
     36	u32 straps = self->straps;
     37	u32 fuses = self->fuses;
     38	unsigned long disabled;
     39	u32 ae_disable;
     40	int accel;
     41
     42	/* If an accel is disabled, then disable the corresponding two AEs */
     43	disabled = ~get_accel_mask(self) & ADF_C3XXX_ACCELERATORS_MASK;
     44	ae_disable = BIT(1) | BIT(0);
     45	for_each_set_bit(accel, &disabled, ADF_C3XXX_MAX_ACCELERATORS)
     46		straps |= ae_disable << (accel << 1);
     47
     48	return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;
     49}
     50
     51static u32 get_misc_bar_id(struct adf_hw_device_data *self)
     52{
     53	return ADF_C3XXX_PMISC_BAR;
     54}
     55
     56static u32 get_etr_bar_id(struct adf_hw_device_data *self)
     57{
     58	return ADF_C3XXX_ETR_BAR;
     59}
     60
     61static u32 get_sram_bar_id(struct adf_hw_device_data *self)
     62{
     63	return ADF_C3XXX_SRAM_BAR;
     64}
     65
     66static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
     67{
     68	int aes = self->get_num_aes(self);
     69
     70	if (aes == 6)
     71		return DEV_SKU_4;
     72
     73	return DEV_SKU_UNKNOWN;
     74}
     75
     76static const u32 *adf_get_arbiter_mapping(void)
     77{
     78	return thrd_to_arb_map;
     79}
     80
     81static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
     82{
     83	adf_gen2_cfg_iov_thds(accel_dev, enable,
     84			      ADF_C3XXX_AE2FUNC_MAP_GRP_A_NUM_REGS,
     85			      ADF_C3XXX_AE2FUNC_MAP_GRP_B_NUM_REGS);
     86}
     87
     88void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
     89{
     90	hw_data->dev_class = &c3xxx_class;
     91	hw_data->instance_id = c3xxx_class.instances++;
     92	hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;
     93	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
     94	hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;
     95	hw_data->num_logical_accel = 1;
     96	hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
     97	hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
     98	hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
     99	hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
    100	hw_data->alloc_irq = adf_isr_resource_alloc;
    101	hw_data->free_irq = adf_isr_resource_free;
    102	hw_data->enable_error_correction = adf_gen2_enable_error_correction;
    103	hw_data->get_accel_mask = get_accel_mask;
    104	hw_data->get_ae_mask = get_ae_mask;
    105	hw_data->get_accel_cap = adf_gen2_get_accel_cap;
    106	hw_data->get_num_accels = adf_gen2_get_num_accels;
    107	hw_data->get_num_aes = adf_gen2_get_num_aes;
    108	hw_data->get_sram_bar_id = get_sram_bar_id;
    109	hw_data->get_etr_bar_id = get_etr_bar_id;
    110	hw_data->get_misc_bar_id = get_misc_bar_id;
    111	hw_data->get_admin_info = adf_gen2_get_admin_info;
    112	hw_data->get_arb_info = adf_gen2_get_arb_info;
    113	hw_data->get_sku = get_sku;
    114	hw_data->fw_name = ADF_C3XXX_FW;
    115	hw_data->fw_mmp_name = ADF_C3XXX_MMP;
    116	hw_data->init_admin_comms = adf_init_admin_comms;
    117	hw_data->exit_admin_comms = adf_exit_admin_comms;
    118	hw_data->configure_iov_threads = configure_iov_threads;
    119	hw_data->send_admin_init = adf_send_admin_init;
    120	hw_data->init_arb = adf_init_arb;
    121	hw_data->exit_arb = adf_exit_arb;
    122	hw_data->get_arb_mapping = adf_get_arbiter_mapping;
    123	hw_data->enable_ints = adf_gen2_enable_ints;
    124	hw_data->reset_device = adf_reset_flr;
    125	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
    126	hw_data->disable_iov = adf_disable_sriov;
    127
    128	adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
    129	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
    130}
    131
    132void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
    133{
    134	hw_data->dev_class->instances--;
    135}