cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cxlpci.h (2642B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
      3#ifndef __CXL_PCI_H__
      4#define __CXL_PCI_H__
      5#include <linux/pci.h>
      6#include "cxl.h"
      7
      8#define CXL_MEMORY_PROGIF	0x10
      9
     10/*
     11 * See section 8.1 Configuration Space Registers in the CXL 2.0
     12 * Specification. Names are taken straight from the specification with "CXL" and
     13 * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
     14 */
     15#define PCI_DVSEC_HEADER1_LENGTH_MASK	GENMASK(31, 20)
     16#define PCI_DVSEC_VENDOR_ID_CXL		0x1E98
     17
     18/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
     19#define CXL_DVSEC_PCIE_DEVICE					0
     20#define   CXL_DVSEC_CAP_OFFSET		0xA
     21#define     CXL_DVSEC_MEM_CAPABLE	BIT(2)
     22#define     CXL_DVSEC_HDM_COUNT_MASK	GENMASK(5, 4)
     23#define   CXL_DVSEC_CTRL_OFFSET		0xC
     24#define     CXL_DVSEC_MEM_ENABLE	BIT(2)
     25#define   CXL_DVSEC_RANGE_SIZE_HIGH(i)	(0x18 + (i * 0x10))
     26#define   CXL_DVSEC_RANGE_SIZE_LOW(i)	(0x1C + (i * 0x10))
     27#define     CXL_DVSEC_MEM_INFO_VALID	BIT(0)
     28#define     CXL_DVSEC_MEM_ACTIVE	BIT(1)
     29#define     CXL_DVSEC_MEM_SIZE_LOW_MASK	GENMASK(31, 28)
     30#define   CXL_DVSEC_RANGE_BASE_HIGH(i)	(0x20 + (i * 0x10))
     31#define   CXL_DVSEC_RANGE_BASE_LOW(i)	(0x24 + (i * 0x10))
     32#define     CXL_DVSEC_MEM_BASE_LOW_MASK	GENMASK(31, 28)
     33
     34/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
     35#define CXL_DVSEC_FUNCTION_MAP					2
     36
     37/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
     38#define CXL_DVSEC_PORT_EXTENSIONS				3
     39
     40/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
     41#define CXL_DVSEC_PORT_GPF					4
     42
     43/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
     44#define CXL_DVSEC_DEVICE_GPF					5
     45
     46/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
     47#define CXL_DVSEC_PCIE_FLEXBUS_PORT				7
     48
     49/* CXL 2.0 8.1.9: Register Locator DVSEC */
     50#define CXL_DVSEC_REG_LOCATOR					8
     51#define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET			0xC
     52#define     CXL_DVSEC_REG_LOCATOR_BIR_MASK			GENMASK(2, 0)
     53#define	    CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK			GENMASK(15, 8)
     54#define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK		GENMASK(31, 16)
     55
     56/* Register Block Identifier (RBI) */
     57enum cxl_regloc_type {
     58	CXL_REGLOC_RBI_EMPTY = 0,
     59	CXL_REGLOC_RBI_COMPONENT,
     60	CXL_REGLOC_RBI_VIRT,
     61	CXL_REGLOC_RBI_MEMDEV,
     62	CXL_REGLOC_RBI_TYPES
     63};
     64
     65static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
     66						 struct cxl_register_map *map)
     67{
     68	if (map->block_offset == U64_MAX)
     69		return CXL_RESOURCE_NONE;
     70
     71	return pci_resource_start(pdev, map->barno) + map->block_offset;
     72}
     73
     74int devm_cxl_port_enumerate_dports(struct cxl_port *port);
     75struct cxl_dev_state;
     76int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
     77#endif /* __CXL_PCI_H__ */