cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mem.c (3851B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
      3#include <linux/device.h>
      4#include <linux/module.h>
      5#include <linux/pci.h>
      6
      7#include "cxlmem.h"
      8#include "cxlpci.h"
      9
     10/**
     11 * DOC: cxl mem
     12 *
     13 * CXL memory endpoint devices and switches are CXL capable devices that are
     14 * participating in CXL.mem protocol. Their functionality builds on top of the
     15 * CXL.io protocol that allows enumerating and configuring components via
     16 * standard PCI mechanisms.
     17 *
     18 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
     19 * capability. With the detection of a CXL capable endpoint, the driver will
     20 * walk up to find the platform specific port it is connected to, and determine
     21 * if there are intervening switches in the path. If there are switches, a
     22 * secondary action is to enumerate those (implemented in cxl_core). Finally the
     23 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
     24 * in higher level operations.
     25 */
     26
     27static int create_endpoint(struct cxl_memdev *cxlmd,
     28			   struct cxl_port *parent_port)
     29{
     30	struct cxl_dev_state *cxlds = cxlmd->cxlds;
     31	struct cxl_port *endpoint;
     32	int rc;
     33
     34	endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
     35				     cxlds->component_reg_phys, parent_port);
     36	if (IS_ERR(endpoint))
     37		return PTR_ERR(endpoint);
     38
     39	dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
     40
     41	rc = cxl_endpoint_autoremove(cxlmd, endpoint);
     42	if (rc)
     43		return rc;
     44
     45	if (!endpoint->dev.driver) {
     46		dev_err(&cxlmd->dev, "%s failed probe\n",
     47			dev_name(&endpoint->dev));
     48		return -ENXIO;
     49	}
     50
     51	return 0;
     52}
     53
     54static void enable_suspend(void *data)
     55{
     56	cxl_mem_active_dec();
     57}
     58
     59static int cxl_mem_probe(struct device *dev)
     60{
     61	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
     62	struct cxl_port *parent_port;
     63	int rc;
     64
     65	/*
     66	 * Someone is trying to reattach this device after it lost its port
     67	 * connection (an endpoint port previously registered by this memdev was
     68	 * disabled). This racy check is ok because if the port is still gone,
     69	 * no harm done, and if the port hierarchy comes back it will re-trigger
     70	 * this probe. Port rescan and memdev detach work share the same
     71	 * single-threaded workqueue.
     72	 */
     73	if (work_pending(&cxlmd->detach_work))
     74		return -EBUSY;
     75
     76	rc = devm_cxl_enumerate_ports(cxlmd);
     77	if (rc)
     78		return rc;
     79
     80	parent_port = cxl_mem_find_port(cxlmd);
     81	if (!parent_port) {
     82		dev_err(dev, "CXL port topology not found\n");
     83		return -ENXIO;
     84	}
     85
     86	device_lock(&parent_port->dev);
     87	if (!parent_port->dev.driver) {
     88		dev_err(dev, "CXL port topology %s not enabled\n",
     89			dev_name(&parent_port->dev));
     90		rc = -ENXIO;
     91		goto unlock;
     92	}
     93
     94	rc = create_endpoint(cxlmd, parent_port);
     95unlock:
     96	device_unlock(&parent_port->dev);
     97	put_device(&parent_port->dev);
     98	if (rc)
     99		return rc;
    100
    101	/*
    102	 * The kernel may be operating out of CXL memory on this device,
    103	 * there is no spec defined way to determine whether this device
    104	 * preserves contents over suspend, and there is no simple way
    105	 * to arrange for the suspend image to avoid CXL memory which
    106	 * would setup a circular dependency between PCI resume and save
    107	 * state restoration.
    108	 *
    109	 * TODO: support suspend when all the regions this device is
    110	 * hosting are locked and covered by the system address map,
    111	 * i.e. platform firmware owns restoring the HDM configuration
    112	 * that it locked.
    113	 */
    114	cxl_mem_active_inc();
    115	return devm_add_action_or_reset(dev, enable_suspend, NULL);
    116}
    117
    118static struct cxl_driver cxl_mem_driver = {
    119	.name = "cxl_mem",
    120	.probe = cxl_mem_probe,
    121	.id = CXL_DEVICE_MEMORY_EXPANDER,
    122};
    123
    124module_cxl_driver(cxl_mem_driver);
    125
    126MODULE_LICENSE("GPL v2");
    127MODULE_IMPORT_NS(CXL);
    128MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
    129/*
    130 * create_endpoint() wants to validate port driver attach immediately after
    131 * endpoint registration.
    132 */
    133MODULE_SOFTDEP("pre: cxl_port");