cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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mmp_tdma.c (19051B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Driver For Marvell Two-channel DMA Engine
      4 *
      5 * Copyright: Marvell International Ltd.
      6 */
      7
      8#include <linux/err.h>
      9#include <linux/module.h>
     10#include <linux/init.h>
     11#include <linux/types.h>
     12#include <linux/interrupt.h>
     13#include <linux/dma-mapping.h>
     14#include <linux/slab.h>
     15#include <linux/dmaengine.h>
     16#include <linux/platform_device.h>
     17#include <linux/device.h>
     18#include <linux/platform_data/dma-mmp_tdma.h>
     19#include <linux/of_device.h>
     20#include <linux/of_dma.h>
     21
     22#include "dmaengine.h"
     23
     24/*
     25 * Two-Channel DMA registers
     26 */
     27#define TDBCR		0x00	/* Byte Count */
     28#define TDSAR		0x10	/* Src Addr */
     29#define TDDAR		0x20	/* Dst Addr */
     30#define TDNDPR		0x30	/* Next Desc */
     31#define TDCR		0x40	/* Control */
     32#define TDCP		0x60	/* Priority*/
     33#define TDCDPR		0x70	/* Current Desc */
     34#define TDIMR		0x80	/* Int Mask */
     35#define TDISR		0xa0	/* Int Status */
     36
     37/* Two-Channel DMA Control Register */
     38#define TDCR_SSZ_8_BITS		(0x0 << 22)	/* Sample Size */
     39#define TDCR_SSZ_12_BITS	(0x1 << 22)
     40#define TDCR_SSZ_16_BITS	(0x2 << 22)
     41#define TDCR_SSZ_20_BITS	(0x3 << 22)
     42#define TDCR_SSZ_24_BITS	(0x4 << 22)
     43#define TDCR_SSZ_32_BITS	(0x5 << 22)
     44#define TDCR_SSZ_SHIFT		(0x1 << 22)
     45#define TDCR_SSZ_MASK		(0x7 << 22)
     46#define TDCR_SSPMOD		(0x1 << 21)	/* SSP MOD */
     47#define TDCR_ABR		(0x1 << 20)	/* Channel Abort */
     48#define TDCR_CDE		(0x1 << 17)	/* Close Desc Enable */
     49#define TDCR_PACKMOD		(0x1 << 16)	/* Pack Mode (ADMA Only) */
     50#define TDCR_CHANACT		(0x1 << 14)	/* Channel Active */
     51#define TDCR_FETCHND		(0x1 << 13)	/* Fetch Next Desc */
     52#define TDCR_CHANEN		(0x1 << 12)	/* Channel Enable */
     53#define TDCR_INTMODE		(0x1 << 10)	/* Interrupt Mode */
     54#define TDCR_CHAINMOD		(0x1 << 9)	/* Chain Mode */
     55#define TDCR_BURSTSZ_MSK	(0x7 << 6)	/* Burst Size */
     56#define TDCR_BURSTSZ_4B		(0x0 << 6)
     57#define TDCR_BURSTSZ_8B		(0x1 << 6)
     58#define TDCR_BURSTSZ_16B	(0x3 << 6)
     59#define TDCR_BURSTSZ_32B	(0x6 << 6)
     60#define TDCR_BURSTSZ_64B	(0x7 << 6)
     61#define TDCR_BURSTSZ_SQU_1B		(0x5 << 6)
     62#define TDCR_BURSTSZ_SQU_2B		(0x6 << 6)
     63#define TDCR_BURSTSZ_SQU_4B		(0x0 << 6)
     64#define TDCR_BURSTSZ_SQU_8B		(0x1 << 6)
     65#define TDCR_BURSTSZ_SQU_16B	(0x3 << 6)
     66#define TDCR_BURSTSZ_SQU_32B	(0x7 << 6)
     67#define TDCR_BURSTSZ_128B	(0x5 << 6)
     68#define TDCR_DSTDIR_MSK		(0x3 << 4)	/* Dst Direction */
     69#define TDCR_DSTDIR_ADDR_HOLD	(0x2 << 4)	/* Dst Addr Hold */
     70#define TDCR_DSTDIR_ADDR_INC	(0x0 << 4)	/* Dst Addr Increment */
     71#define TDCR_SRCDIR_MSK		(0x3 << 2)	/* Src Direction */
     72#define TDCR_SRCDIR_ADDR_HOLD	(0x2 << 2)	/* Src Addr Hold */
     73#define TDCR_SRCDIR_ADDR_INC	(0x0 << 2)	/* Src Addr Increment */
     74#define TDCR_DSTDESCCONT	(0x1 << 1)
     75#define TDCR_SRCDESTCONT	(0x1 << 0)
     76
     77/* Two-Channel DMA Int Mask Register */
     78#define TDIMR_COMP		(0x1 << 0)
     79
     80/* Two-Channel DMA Int Status Register */
     81#define TDISR_COMP		(0x1 << 0)
     82
     83/*
     84 * Two-Channel DMA Descriptor Struct
     85 * NOTE: desc's buf must be aligned to 16 bytes.
     86 */
     87struct mmp_tdma_desc {
     88	u32 byte_cnt;
     89	u32 src_addr;
     90	u32 dst_addr;
     91	u32 nxt_desc;
     92};
     93
     94enum mmp_tdma_type {
     95	MMP_AUD_TDMA = 0,
     96	PXA910_SQU,
     97};
     98
     99#define TDMA_MAX_XFER_BYTES    SZ_64K
    100
    101struct mmp_tdma_chan {
    102	struct device			*dev;
    103	struct dma_chan			chan;
    104	struct dma_async_tx_descriptor	desc;
    105	struct tasklet_struct		tasklet;
    106
    107	struct mmp_tdma_desc		*desc_arr;
    108	dma_addr_t			desc_arr_phys;
    109	int				desc_num;
    110	enum dma_transfer_direction	dir;
    111	dma_addr_t			dev_addr;
    112	u32				burst_sz;
    113	enum dma_slave_buswidth		buswidth;
    114	enum dma_status			status;
    115	struct dma_slave_config		slave_config;
    116
    117	int				idx;
    118	enum mmp_tdma_type		type;
    119	int				irq;
    120	void __iomem			*reg_base;
    121
    122	size_t				buf_len;
    123	size_t				period_len;
    124	size_t				pos;
    125
    126	struct gen_pool			*pool;
    127};
    128
    129#define TDMA_CHANNEL_NUM 2
    130struct mmp_tdma_device {
    131	struct device			*dev;
    132	void __iomem			*base;
    133	struct dma_device		device;
    134	struct mmp_tdma_chan		*tdmac[TDMA_CHANNEL_NUM];
    135};
    136
    137#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
    138
    139static int mmp_tdma_config_write(struct dma_chan *chan,
    140				 enum dma_transfer_direction dir,
    141				 struct dma_slave_config *dmaengine_cfg);
    142
    143static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
    144{
    145	writel(phys, tdmac->reg_base + TDNDPR);
    146	writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
    147					tdmac->reg_base + TDCR);
    148}
    149
    150static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
    151{
    152	if (enable)
    153		writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
    154	else
    155		writel(0, tdmac->reg_base + TDIMR);
    156}
    157
    158static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
    159{
    160	/* enable dma chan */
    161	writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
    162					tdmac->reg_base + TDCR);
    163	tdmac->status = DMA_IN_PROGRESS;
    164}
    165
    166static int mmp_tdma_disable_chan(struct dma_chan *chan)
    167{
    168	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    169	u32 tdcr;
    170
    171	tdcr = readl(tdmac->reg_base + TDCR);
    172	tdcr |= TDCR_ABR;
    173	tdcr &= ~TDCR_CHANEN;
    174	writel(tdcr, tdmac->reg_base + TDCR);
    175
    176	tdmac->status = DMA_COMPLETE;
    177
    178	return 0;
    179}
    180
    181static int mmp_tdma_resume_chan(struct dma_chan *chan)
    182{
    183	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    184
    185	writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
    186					tdmac->reg_base + TDCR);
    187	tdmac->status = DMA_IN_PROGRESS;
    188
    189	return 0;
    190}
    191
    192static int mmp_tdma_pause_chan(struct dma_chan *chan)
    193{
    194	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    195
    196	writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
    197					tdmac->reg_base + TDCR);
    198	tdmac->status = DMA_PAUSED;
    199
    200	return 0;
    201}
    202
    203static int mmp_tdma_config_chan(struct dma_chan *chan)
    204{
    205	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    206	unsigned int tdcr = 0;
    207
    208	mmp_tdma_disable_chan(chan);
    209
    210	if (tdmac->dir == DMA_MEM_TO_DEV)
    211		tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
    212	else if (tdmac->dir == DMA_DEV_TO_MEM)
    213		tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
    214
    215	if (tdmac->type == MMP_AUD_TDMA) {
    216		tdcr |= TDCR_PACKMOD;
    217
    218		switch (tdmac->burst_sz) {
    219		case 4:
    220			tdcr |= TDCR_BURSTSZ_4B;
    221			break;
    222		case 8:
    223			tdcr |= TDCR_BURSTSZ_8B;
    224			break;
    225		case 16:
    226			tdcr |= TDCR_BURSTSZ_16B;
    227			break;
    228		case 32:
    229			tdcr |= TDCR_BURSTSZ_32B;
    230			break;
    231		case 64:
    232			tdcr |= TDCR_BURSTSZ_64B;
    233			break;
    234		case 128:
    235			tdcr |= TDCR_BURSTSZ_128B;
    236			break;
    237		default:
    238			dev_err(tdmac->dev, "unknown burst size.\n");
    239			return -EINVAL;
    240		}
    241
    242		switch (tdmac->buswidth) {
    243		case DMA_SLAVE_BUSWIDTH_1_BYTE:
    244			tdcr |= TDCR_SSZ_8_BITS;
    245			break;
    246		case DMA_SLAVE_BUSWIDTH_2_BYTES:
    247			tdcr |= TDCR_SSZ_16_BITS;
    248			break;
    249		case DMA_SLAVE_BUSWIDTH_4_BYTES:
    250			tdcr |= TDCR_SSZ_32_BITS;
    251			break;
    252		default:
    253			dev_err(tdmac->dev, "unknown bus size.\n");
    254			return -EINVAL;
    255		}
    256	} else if (tdmac->type == PXA910_SQU) {
    257		tdcr |= TDCR_SSPMOD;
    258
    259		switch (tdmac->burst_sz) {
    260		case 1:
    261			tdcr |= TDCR_BURSTSZ_SQU_1B;
    262			break;
    263		case 2:
    264			tdcr |= TDCR_BURSTSZ_SQU_2B;
    265			break;
    266		case 4:
    267			tdcr |= TDCR_BURSTSZ_SQU_4B;
    268			break;
    269		case 8:
    270			tdcr |= TDCR_BURSTSZ_SQU_8B;
    271			break;
    272		case 16:
    273			tdcr |= TDCR_BURSTSZ_SQU_16B;
    274			break;
    275		case 32:
    276			tdcr |= TDCR_BURSTSZ_SQU_32B;
    277			break;
    278		default:
    279			dev_err(tdmac->dev, "unknown burst size.\n");
    280			return -EINVAL;
    281		}
    282	}
    283
    284	writel(tdcr, tdmac->reg_base + TDCR);
    285	return 0;
    286}
    287
    288static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
    289{
    290	u32 reg = readl(tdmac->reg_base + TDISR);
    291
    292	if (reg & TDISR_COMP) {
    293		/* clear irq */
    294		reg &= ~TDISR_COMP;
    295		writel(reg, tdmac->reg_base + TDISR);
    296
    297		return 0;
    298	}
    299	return -EAGAIN;
    300}
    301
    302static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac)
    303{
    304	size_t reg;
    305
    306	if (tdmac->idx == 0) {
    307		reg = __raw_readl(tdmac->reg_base + TDSAR);
    308		reg -= tdmac->desc_arr[0].src_addr;
    309	} else if (tdmac->idx == 1) {
    310		reg = __raw_readl(tdmac->reg_base + TDDAR);
    311		reg -= tdmac->desc_arr[0].dst_addr;
    312	} else
    313		return -EINVAL;
    314
    315	return reg;
    316}
    317
    318static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
    319{
    320	struct mmp_tdma_chan *tdmac = dev_id;
    321
    322	if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
    323		tasklet_schedule(&tdmac->tasklet);
    324		return IRQ_HANDLED;
    325	} else
    326		return IRQ_NONE;
    327}
    328
    329static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
    330{
    331	struct mmp_tdma_device *tdev = dev_id;
    332	int i, ret;
    333	int irq_num = 0;
    334
    335	for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
    336		struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
    337
    338		ret = mmp_tdma_chan_handler(irq, tdmac);
    339		if (ret == IRQ_HANDLED)
    340			irq_num++;
    341	}
    342
    343	if (irq_num)
    344		return IRQ_HANDLED;
    345	else
    346		return IRQ_NONE;
    347}
    348
    349static void dma_do_tasklet(struct tasklet_struct *t)
    350{
    351	struct mmp_tdma_chan *tdmac = from_tasklet(tdmac, t, tasklet);
    352
    353	dmaengine_desc_get_callback_invoke(&tdmac->desc, NULL);
    354}
    355
    356static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
    357{
    358	struct gen_pool *gpool;
    359	int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
    360
    361	gpool = tdmac->pool;
    362	if (gpool && tdmac->desc_arr)
    363		gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
    364				size);
    365	tdmac->desc_arr = NULL;
    366	if (tdmac->status == DMA_ERROR)
    367		tdmac->status = DMA_COMPLETE;
    368
    369	return;
    370}
    371
    372static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
    373{
    374	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
    375
    376	mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
    377
    378	return 0;
    379}
    380
    381static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
    382{
    383	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    384	int ret;
    385
    386	dma_async_tx_descriptor_init(&tdmac->desc, chan);
    387	tdmac->desc.tx_submit = mmp_tdma_tx_submit;
    388
    389	if (tdmac->irq) {
    390		ret = devm_request_irq(tdmac->dev, tdmac->irq,
    391			mmp_tdma_chan_handler, 0, "tdma", tdmac);
    392		if (ret)
    393			return ret;
    394	}
    395	return 1;
    396}
    397
    398static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
    399{
    400	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    401
    402	if (tdmac->irq)
    403		devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
    404	mmp_tdma_free_descriptor(tdmac);
    405	return;
    406}
    407
    408static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
    409{
    410	struct gen_pool *gpool;
    411	int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
    412
    413	gpool = tdmac->pool;
    414	if (!gpool)
    415		return NULL;
    416
    417	tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
    418
    419	return tdmac->desc_arr;
    420}
    421
    422static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
    423		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
    424		size_t period_len, enum dma_transfer_direction direction,
    425		unsigned long flags)
    426{
    427	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    428	struct mmp_tdma_desc *desc;
    429	int num_periods = buf_len / period_len;
    430	int i = 0, buf = 0;
    431
    432	if (!is_slave_direction(direction)) {
    433		dev_err(tdmac->dev, "unsupported transfer direction\n");
    434		return NULL;
    435	}
    436
    437	if (tdmac->status != DMA_COMPLETE) {
    438		dev_err(tdmac->dev, "controller busy");
    439		return NULL;
    440	}
    441
    442	if (period_len > TDMA_MAX_XFER_BYTES) {
    443		dev_err(tdmac->dev,
    444				"maximum period size exceeded: %zu > %d\n",
    445				period_len, TDMA_MAX_XFER_BYTES);
    446		goto err_out;
    447	}
    448
    449	tdmac->status = DMA_IN_PROGRESS;
    450	tdmac->desc_num = num_periods;
    451	desc = mmp_tdma_alloc_descriptor(tdmac);
    452	if (!desc)
    453		goto err_out;
    454
    455	if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
    456		goto err_out;
    457
    458	while (buf < buf_len) {
    459		desc = &tdmac->desc_arr[i];
    460
    461		if (i + 1 == num_periods)
    462			desc->nxt_desc = tdmac->desc_arr_phys;
    463		else
    464			desc->nxt_desc = tdmac->desc_arr_phys +
    465				sizeof(*desc) * (i + 1);
    466
    467		if (direction == DMA_MEM_TO_DEV) {
    468			desc->src_addr = dma_addr;
    469			desc->dst_addr = tdmac->dev_addr;
    470		} else {
    471			desc->src_addr = tdmac->dev_addr;
    472			desc->dst_addr = dma_addr;
    473		}
    474		desc->byte_cnt = period_len;
    475		dma_addr += period_len;
    476		buf += period_len;
    477		i++;
    478	}
    479
    480	/* enable interrupt */
    481	if (flags & DMA_PREP_INTERRUPT)
    482		mmp_tdma_enable_irq(tdmac, true);
    483
    484	tdmac->buf_len = buf_len;
    485	tdmac->period_len = period_len;
    486	tdmac->pos = 0;
    487
    488	return &tdmac->desc;
    489
    490err_out:
    491	tdmac->status = DMA_ERROR;
    492	return NULL;
    493}
    494
    495static int mmp_tdma_terminate_all(struct dma_chan *chan)
    496{
    497	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    498
    499	mmp_tdma_disable_chan(chan);
    500	/* disable interrupt */
    501	mmp_tdma_enable_irq(tdmac, false);
    502
    503	return 0;
    504}
    505
    506static int mmp_tdma_config(struct dma_chan *chan,
    507			   struct dma_slave_config *dmaengine_cfg)
    508{
    509	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    510
    511	memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
    512
    513	return 0;
    514}
    515
    516static int mmp_tdma_config_write(struct dma_chan *chan,
    517				 enum dma_transfer_direction dir,
    518				 struct dma_slave_config *dmaengine_cfg)
    519{
    520	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    521
    522	if (dir == DMA_DEV_TO_MEM) {
    523		tdmac->dev_addr = dmaengine_cfg->src_addr;
    524		tdmac->burst_sz = dmaengine_cfg->src_maxburst;
    525		tdmac->buswidth = dmaengine_cfg->src_addr_width;
    526	} else {
    527		tdmac->dev_addr = dmaengine_cfg->dst_addr;
    528		tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
    529		tdmac->buswidth = dmaengine_cfg->dst_addr_width;
    530	}
    531	tdmac->dir = dir;
    532
    533	return mmp_tdma_config_chan(chan);
    534}
    535
    536static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
    537			dma_cookie_t cookie, struct dma_tx_state *txstate)
    538{
    539	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    540
    541	tdmac->pos = mmp_tdma_get_pos(tdmac);
    542	dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
    543			 tdmac->buf_len - tdmac->pos);
    544
    545	return tdmac->status;
    546}
    547
    548static void mmp_tdma_issue_pending(struct dma_chan *chan)
    549{
    550	struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
    551
    552	mmp_tdma_enable_chan(tdmac);
    553}
    554
    555static int mmp_tdma_remove(struct platform_device *pdev)
    556{
    557	if (pdev->dev.of_node)
    558		of_dma_controller_free(pdev->dev.of_node);
    559
    560	return 0;
    561}
    562
    563static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
    564					int idx, int irq,
    565					int type, struct gen_pool *pool)
    566{
    567	struct mmp_tdma_chan *tdmac;
    568
    569	if (idx >= TDMA_CHANNEL_NUM) {
    570		dev_err(tdev->dev, "too many channels for device!\n");
    571		return -EINVAL;
    572	}
    573
    574	/* alloc channel */
    575	tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
    576	if (!tdmac)
    577		return -ENOMEM;
    578
    579	if (irq)
    580		tdmac->irq = irq;
    581	tdmac->dev	   = tdev->dev;
    582	tdmac->chan.device = &tdev->device;
    583	tdmac->idx	   = idx;
    584	tdmac->type	   = type;
    585	tdmac->reg_base	   = tdev->base + idx * 4;
    586	tdmac->pool	   = pool;
    587	tdmac->status = DMA_COMPLETE;
    588	tdev->tdmac[tdmac->idx] = tdmac;
    589	tasklet_setup(&tdmac->tasklet, dma_do_tasklet);
    590
    591	/* add the channel to tdma_chan list */
    592	list_add_tail(&tdmac->chan.device_node,
    593			&tdev->device.channels);
    594	return 0;
    595}
    596
    597struct mmp_tdma_filter_param {
    598	unsigned int chan_id;
    599};
    600
    601static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
    602{
    603	struct mmp_tdma_filter_param *param = fn_param;
    604
    605	if (chan->chan_id != param->chan_id)
    606		return false;
    607
    608	return true;
    609}
    610
    611static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
    612			       struct of_dma *ofdma)
    613{
    614	struct mmp_tdma_device *tdev = ofdma->of_dma_data;
    615	dma_cap_mask_t mask = tdev->device.cap_mask;
    616	struct mmp_tdma_filter_param param;
    617
    618	if (dma_spec->args_count != 1)
    619		return NULL;
    620
    621	param.chan_id = dma_spec->args[0];
    622
    623	if (param.chan_id >= TDMA_CHANNEL_NUM)
    624		return NULL;
    625
    626	return __dma_request_channel(&mask, mmp_tdma_filter_fn, &param,
    627				     ofdma->of_node);
    628}
    629
    630static const struct of_device_id mmp_tdma_dt_ids[] = {
    631	{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
    632	{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
    633	{}
    634};
    635MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
    636
    637static int mmp_tdma_probe(struct platform_device *pdev)
    638{
    639	enum mmp_tdma_type type;
    640	const struct of_device_id *of_id;
    641	struct mmp_tdma_device *tdev;
    642	struct resource *iores;
    643	int i, ret;
    644	int irq = 0, irq_num = 0;
    645	int chan_num = TDMA_CHANNEL_NUM;
    646	struct gen_pool *pool = NULL;
    647
    648	of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
    649	if (of_id)
    650		type = (enum mmp_tdma_type) of_id->data;
    651	else
    652		type = platform_get_device_id(pdev)->driver_data;
    653
    654	/* always have couple channels */
    655	tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
    656	if (!tdev)
    657		return -ENOMEM;
    658
    659	tdev->dev = &pdev->dev;
    660
    661	for (i = 0; i < chan_num; i++) {
    662		if (platform_get_irq(pdev, i) > 0)
    663			irq_num++;
    664	}
    665
    666	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    667	tdev->base = devm_ioremap_resource(&pdev->dev, iores);
    668	if (IS_ERR(tdev->base))
    669		return PTR_ERR(tdev->base);
    670
    671	INIT_LIST_HEAD(&tdev->device.channels);
    672
    673	if (pdev->dev.of_node)
    674		pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0);
    675	else
    676		pool = sram_get_gpool("asram");
    677	if (!pool) {
    678		dev_err(&pdev->dev, "asram pool not available\n");
    679		return -ENOMEM;
    680	}
    681
    682	if (irq_num != chan_num) {
    683		irq = platform_get_irq(pdev, 0);
    684		ret = devm_request_irq(&pdev->dev, irq,
    685			mmp_tdma_int_handler, IRQF_SHARED, "tdma", tdev);
    686		if (ret)
    687			return ret;
    688	}
    689
    690	/* initialize channel parameters */
    691	for (i = 0; i < chan_num; i++) {
    692		irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
    693		ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
    694		if (ret)
    695			return ret;
    696	}
    697
    698	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
    699	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
    700	tdev->device.dev = &pdev->dev;
    701	tdev->device.device_alloc_chan_resources =
    702					mmp_tdma_alloc_chan_resources;
    703	tdev->device.device_free_chan_resources =
    704					mmp_tdma_free_chan_resources;
    705	tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
    706	tdev->device.device_tx_status = mmp_tdma_tx_status;
    707	tdev->device.device_issue_pending = mmp_tdma_issue_pending;
    708	tdev->device.device_config = mmp_tdma_config;
    709	tdev->device.device_pause = mmp_tdma_pause_chan;
    710	tdev->device.device_resume = mmp_tdma_resume_chan;
    711	tdev->device.device_terminate_all = mmp_tdma_terminate_all;
    712	tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
    713
    714	tdev->device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
    715	if (type == MMP_AUD_TDMA) {
    716		tdev->device.max_burst = SZ_128;
    717		tdev->device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
    718		tdev->device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
    719	} else if (type == PXA910_SQU) {
    720		tdev->device.max_burst = SZ_32;
    721	}
    722	tdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
    723	tdev->device.descriptor_reuse = true;
    724
    725	dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
    726	platform_set_drvdata(pdev, tdev);
    727
    728	ret = dmaenginem_async_device_register(&tdev->device);
    729	if (ret) {
    730		dev_err(tdev->device.dev, "unable to register\n");
    731		return ret;
    732	}
    733
    734	if (pdev->dev.of_node) {
    735		ret = of_dma_controller_register(pdev->dev.of_node,
    736							mmp_tdma_xlate, tdev);
    737		if (ret) {
    738			dev_err(tdev->device.dev,
    739				"failed to register controller\n");
    740			return ret;
    741		}
    742	}
    743
    744	dev_info(tdev->device.dev, "initialized\n");
    745	return 0;
    746}
    747
    748static const struct platform_device_id mmp_tdma_id_table[] = {
    749	{ "mmp-adma",	MMP_AUD_TDMA },
    750	{ "pxa910-squ",	PXA910_SQU },
    751	{ },
    752};
    753
    754static struct platform_driver mmp_tdma_driver = {
    755	.driver		= {
    756		.name	= "mmp-tdma",
    757		.of_match_table = mmp_tdma_dt_ids,
    758	},
    759	.id_table	= mmp_tdma_id_table,
    760	.probe		= mmp_tdma_probe,
    761	.remove		= mmp_tdma_remove,
    762};
    763
    764module_platform_driver(mmp_tdma_driver);
    765
    766MODULE_LICENSE("GPL");
    767MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
    768MODULE_ALIAS("platform:mmp-tdma");
    769MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
    770MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");