cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amd8131_edac.h (3169B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
      4 *
      5 * Copyright (c) 2008 Wind River Systems, Inc.
      6 *
      7 * Authors:	Cao Qingtao <qingtao.cao@windriver.com>
      8 * 		Benjamin Walsh <benjamin.walsh@windriver.com>
      9 * 		Hu Yongqi <yongqi.hu@windriver.com>
     10 */
     11
     12#ifndef _AMD8131_EDAC_H_
     13#define _AMD8131_EDAC_H_
     14
     15#define DEVFN_PCIX_BRIDGE_NORTH_A	8
     16#define DEVFN_PCIX_BRIDGE_NORTH_B	16
     17#define DEVFN_PCIX_BRIDGE_SOUTH_A	24
     18#define DEVFN_PCIX_BRIDGE_SOUTH_B	32
     19
     20/************************************************************
     21 *	PCI-X Bridge Status and Command Register, DevA:0x04
     22 ************************************************************/
     23#define REG_STS_CMD	0x04
     24enum sts_cmd_bits {
     25	STS_CMD_SSE	= BIT(30),
     26	STS_CMD_SERREN	= BIT(8)
     27};
     28
     29/************************************************************
     30 *	PCI-X Bridge Interrupt and Bridge Control Register,
     31 ************************************************************/
     32#define REG_INT_CTLR	0x3c
     33enum int_ctlr_bits {
     34	INT_CTLR_DTSE	= BIT(27),
     35	INT_CTLR_DTS	= BIT(26),
     36	INT_CTLR_SERR	= BIT(17),
     37	INT_CTLR_PERR	= BIT(16)
     38};
     39
     40/************************************************************
     41 *	PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
     42 ************************************************************/
     43#define REG_MEM_LIM	0x1c
     44enum mem_limit_bits {
     45	MEM_LIMIT_DPE 	= BIT(31),
     46	MEM_LIMIT_RSE 	= BIT(30),
     47	MEM_LIMIT_RMA 	= BIT(29),
     48	MEM_LIMIT_RTA 	= BIT(28),
     49	MEM_LIMIT_STA	= BIT(27),
     50	MEM_LIMIT_MDPE	= BIT(24),
     51	MEM_LIMIT_MASK	= MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
     52				MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
     53};
     54
     55/************************************************************
     56 *	Link Configuration And Control Register, side A
     57 ************************************************************/
     58#define REG_LNK_CTRL_A	0xc4
     59
     60/************************************************************
     61 *	Link Configuration And Control Register, side B
     62 ************************************************************/
     63#define REG_LNK_CTRL_B  0xc8
     64
     65enum lnk_ctrl_bits {
     66	LNK_CTRL_CRCERR_A	= BIT(9),
     67	LNK_CTRL_CRCERR_B	= BIT(8),
     68	LNK_CTRL_CRCFEN		= BIT(1)
     69};
     70
     71enum pcix_bridge_inst {
     72	NORTH_A = 0,
     73	NORTH_B = 1,
     74	SOUTH_A = 2,
     75	SOUTH_B = 3,
     76	NO_BRIDGE = 4
     77};
     78
     79struct amd8131_dev_info {
     80	int devfn;
     81	enum pcix_bridge_inst inst;
     82	struct pci_dev *dev;
     83	int edac_idx;	/* pci device index */
     84	char *ctl_name;
     85	struct edac_pci_ctl_info *edac_dev;
     86};
     87
     88/*
     89 * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
     90 * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
     91 * four PCIX Bridges on ATCA-6101 altogether.
     92 *
     93 * These PCIX Bridges share the same PCI Device ID and are all of
     94 * Function Zero, they could be discrimated by their pci_dev->devfn.
     95 * They share the same set of init/check/exit methods, and their
     96 * private structures are collected in the devices[] array.
     97 */
     98struct amd8131_info {
     99	u16 err_dev;	/* PCI Device ID for AMD8131 APIC*/
    100	struct amd8131_dev_info *devices;
    101	void (*init)(struct amd8131_dev_info *dev_info);
    102	void (*exit)(struct amd8131_dev_info *dev_info);
    103	void (*check)(struct edac_pci_ctl_info *edac_dev);
    104};
    105
    106#endif /* _AMD8131_EDAC_H_ */
    107