skx_common.h (5139B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. 4 * Originally split out from the skx_edac driver. 5 * 6 * Copyright (c) 2018, Intel Corporation. 7 */ 8 9#ifndef _SKX_COMM_EDAC_H 10#define _SKX_COMM_EDAC_H 11 12#include <linux/bits.h> 13 14#define MSG_SIZE 1024 15 16/* 17 * Debug macros 18 */ 19#define skx_printk(level, fmt, arg...) \ 20 edac_printk(level, "skx", fmt, ##arg) 21 22#define skx_mc_printk(mci, level, fmt, arg...) \ 23 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) 24 25/* 26 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 27 */ 28#define GET_BITFIELD(v, lo, hi) \ 29 (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) 30 31#define SKX_NUM_IMC 2 /* Memory controllers per socket */ 32#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ 33#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ 34 35#define I10NM_NUM_DDR_IMC 4 36#define I10NM_NUM_DDR_CHANNELS 2 37#define I10NM_NUM_DDR_DIMMS 2 38 39#define I10NM_NUM_HBM_IMC 16 40#define I10NM_NUM_HBM_CHANNELS 2 41#define I10NM_NUM_HBM_DIMMS 1 42 43#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC) 44#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS) 45#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) 46 47#define MAX(a, b) ((a) > (b) ? (a) : (b)) 48#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC) 49#define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) 50#define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS) 51 52#define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15) 53#define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i) 54 55/* 56 * Each cpu socket contains some pci devices that provide global 57 * information, and also some that are local to each of the two 58 * memory controllers on the die. 59 */ 60struct skx_dev { 61 struct list_head list; 62 u8 bus[4]; 63 int seg; 64 struct pci_dev *sad_all; 65 struct pci_dev *util_all; 66 struct pci_dev *uracu; /* for i10nm CPU */ 67 struct pci_dev *pcu_cr3; /* for HBM memory detection */ 68 u32 mcroute; 69 struct skx_imc { 70 struct mem_ctl_info *mci; 71 struct pci_dev *mdev; /* for i10nm CPU */ 72 void __iomem *mbase; /* for i10nm CPU */ 73 int chan_mmio_sz; /* for i10nm CPU */ 74 int num_channels; /* channels per memory controller */ 75 int num_dimms; /* dimms per channel */ 76 bool hbm_mc; 77 u8 mc; /* system wide mc# */ 78 u8 lmc; /* socket relative mc# */ 79 u8 src_id, node_id; 80 struct skx_channel { 81 struct pci_dev *cdev; 82 struct pci_dev *edev; 83 u32 retry_rd_err_log_s; 84 u32 retry_rd_err_log_d; 85 struct skx_dimm { 86 u8 close_pg; 87 u8 bank_xor_enable; 88 u8 fine_grain_bank; 89 u8 rowbits; 90 u8 colbits; 91 } dimms[NUM_DIMMS]; 92 } chan[NUM_CHANNELS]; 93 } imc[NUM_IMC]; 94}; 95 96struct skx_pvt { 97 struct skx_imc *imc; 98}; 99 100enum type { 101 SKX, 102 I10NM, 103 SPR 104}; 105 106enum { 107 INDEX_SOCKET, 108 INDEX_MEMCTRL, 109 INDEX_CHANNEL, 110 INDEX_DIMM, 111 INDEX_NM_FIRST, 112 INDEX_NM_MEMCTRL = INDEX_NM_FIRST, 113 INDEX_NM_CHANNEL, 114 INDEX_NM_DIMM, 115 INDEX_MAX 116}; 117 118#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL) 119#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL) 120#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM) 121 122struct decoded_addr { 123 struct skx_dev *dev; 124 u64 addr; 125 int socket; 126 int imc; 127 int channel; 128 u64 chan_addr; 129 int sktways; 130 int chanways; 131 int dimm; 132 int rank; 133 int channel_rank; 134 u64 rank_address; 135 int row; 136 int column; 137 int bank_address; 138 int bank_group; 139}; 140 141struct res_config { 142 enum type type; 143 /* Configuration agent device ID */ 144 unsigned int decs_did; 145 /* Default bus number configuration register offset */ 146 int busno_cfg_offset; 147 /* Per DDR channel memory-mapped I/O size */ 148 int ddr_chan_mmio_sz; 149 /* Per HBM channel memory-mapped I/O size */ 150 int hbm_chan_mmio_sz; 151 bool support_ddr5; 152 /* SAD device number and function number */ 153 unsigned int sad_all_devfn; 154 int sad_all_offset; 155 /* Offsets of retry_rd_err_log registers */ 156 u32 *offsets_scrub; 157 u32 *offsets_demand; 158}; 159 160typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, 161 struct res_config *cfg); 162typedef bool (*skx_decode_f)(struct decoded_addr *res); 163typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err); 164 165int __init skx_adxl_get(void); 166void __exit skx_adxl_put(void); 167void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); 168void skx_set_mem_cfg(bool mem_cfg_2lm); 169 170int skx_get_src_id(struct skx_dev *d, int off, u8 *id); 171int skx_get_node_id(struct skx_dev *d, u8 *id); 172 173int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list); 174 175int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm); 176 177int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, 178 struct skx_imc *imc, int chan, int dimmno, 179 struct res_config *cfg); 180 181int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 182 int chan, int dimmno, const char *mod_str); 183 184int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 185 const char *ctl_name, const char *mod_str, 186 get_dimm_config_f get_dimm_config, 187 struct res_config *cfg); 188 189int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 190 void *data); 191 192void skx_remove(void); 193 194#endif /* _SKX_COMM_EDAC_H */