nosy.h (10007B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Chip register definitions for PCILynx chipset. Based on pcilynx.h 4 * from the Linux 1394 drivers, but modified a bit so the names here 5 * match the specification exactly (even though they have weird names, 6 * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent 7 * reject" etc.) 8 */ 9 10#define PCILYNX_MAX_REGISTER 0xfff 11#define PCILYNX_MAX_MEMORY 0xffff 12 13#define PCI_LATENCY_CACHELINE 0x0c 14 15#define MISC_CONTROL 0x40 16#define MISC_CONTROL_SWRESET (1<<0) 17 18#define SERIAL_EEPROM_CONTROL 0x44 19 20#define PCI_INT_STATUS 0x48 21#define PCI_INT_ENABLE 0x4c 22/* status and enable have identical bit numbers */ 23#define PCI_INT_INT_PEND (1<<31) 24#define PCI_INT_FRC_INT (1<<30) 25#define PCI_INT_SLV_ADR_PERR (1<<28) 26#define PCI_INT_SLV_DAT_PERR (1<<27) 27#define PCI_INT_MST_DAT_PERR (1<<26) 28#define PCI_INT_MST_DEV_TO (1<<25) 29#define PCI_INT_INT_SLV_TO (1<<23) 30#define PCI_INT_AUX_TO (1<<18) 31#define PCI_INT_AUX_INT (1<<17) 32#define PCI_INT_P1394_INT (1<<16) 33#define PCI_INT_DMA4_PCL (1<<9) 34#define PCI_INT_DMA4_HLT (1<<8) 35#define PCI_INT_DMA3_PCL (1<<7) 36#define PCI_INT_DMA3_HLT (1<<6) 37#define PCI_INT_DMA2_PCL (1<<5) 38#define PCI_INT_DMA2_HLT (1<<4) 39#define PCI_INT_DMA1_PCL (1<<3) 40#define PCI_INT_DMA1_HLT (1<<2) 41#define PCI_INT_DMA0_PCL (1<<1) 42#define PCI_INT_DMA0_HLT (1<<0) 43/* all DMA interrupts combined: */ 44#define PCI_INT_DMA_ALL 0x3ff 45 46#define PCI_INT_DMA_HLT(chan) (1 << (chan * 2)) 47#define PCI_INT_DMA_PCL(chan) (1 << (chan * 2 + 1)) 48 49#define LBUS_ADDR 0xb4 50#define LBUS_ADDR_SEL_RAM (0x0<<16) 51#define LBUS_ADDR_SEL_ROM (0x1<<16) 52#define LBUS_ADDR_SEL_AUX (0x2<<16) 53#define LBUS_ADDR_SEL_ZV (0x3<<16) 54 55#define GPIO_CTRL_A 0xb8 56#define GPIO_CTRL_B 0xbc 57#define GPIO_DATA_BASE 0xc0 58 59#define DMA_BREG(base, chan) (base + chan * 0x20) 60#define DMA_SREG(base, chan) (base + chan * 0x10) 61 62#define PCL_NEXT_INVALID (1<<0) 63 64/* transfer commands */ 65#define PCL_CMD_RCV (0x1<<24) 66#define PCL_CMD_RCV_AND_UPDATE (0xa<<24) 67#define PCL_CMD_XMT (0x2<<24) 68#define PCL_CMD_UNFXMT (0xc<<24) 69#define PCL_CMD_PCI_TO_LBUS (0x8<<24) 70#define PCL_CMD_LBUS_TO_PCI (0x9<<24) 71 72/* aux commands */ 73#define PCL_CMD_NOP (0x0<<24) 74#define PCL_CMD_LOAD (0x3<<24) 75#define PCL_CMD_STOREQ (0x4<<24) 76#define PCL_CMD_STORED (0xb<<24) 77#define PCL_CMD_STORE0 (0x5<<24) 78#define PCL_CMD_STORE1 (0x6<<24) 79#define PCL_CMD_COMPARE (0xe<<24) 80#define PCL_CMD_SWAP_COMPARE (0xf<<24) 81#define PCL_CMD_ADD (0xd<<24) 82#define PCL_CMD_BRANCH (0x7<<24) 83 84/* BRANCH condition codes */ 85#define PCL_COND_DMARDY_SET (0x1<<20) 86#define PCL_COND_DMARDY_CLEAR (0x2<<20) 87 88#define PCL_GEN_INTR (1<<19) 89#define PCL_LAST_BUFF (1<<18) 90#define PCL_LAST_CMD (PCL_LAST_BUFF) 91#define PCL_WAITSTAT (1<<17) 92#define PCL_BIGENDIAN (1<<16) 93#define PCL_ISOMODE (1<<12) 94 95#define DMA0_PREV_PCL 0x100 96#define DMA1_PREV_PCL 0x120 97#define DMA2_PREV_PCL 0x140 98#define DMA3_PREV_PCL 0x160 99#define DMA4_PREV_PCL 0x180 100#define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan)) 101 102#define DMA0_CURRENT_PCL 0x104 103#define DMA1_CURRENT_PCL 0x124 104#define DMA2_CURRENT_PCL 0x144 105#define DMA3_CURRENT_PCL 0x164 106#define DMA4_CURRENT_PCL 0x184 107#define DMA_CURRENT_PCL(chan) (DMA_BREG(DMA0_CURRENT_PCL, chan)) 108 109#define DMA0_CHAN_STAT 0x10c 110#define DMA1_CHAN_STAT 0x12c 111#define DMA2_CHAN_STAT 0x14c 112#define DMA3_CHAN_STAT 0x16c 113#define DMA4_CHAN_STAT 0x18c 114#define DMA_CHAN_STAT(chan) (DMA_BREG(DMA0_CHAN_STAT, chan)) 115/* CHAN_STATUS registers share bits */ 116#define DMA_CHAN_STAT_SELFID (1<<31) 117#define DMA_CHAN_STAT_ISOPKT (1<<30) 118#define DMA_CHAN_STAT_PCIERR (1<<29) 119#define DMA_CHAN_STAT_PKTERR (1<<28) 120#define DMA_CHAN_STAT_PKTCMPL (1<<27) 121#define DMA_CHAN_STAT_SPECIALACK (1<<14) 122 123#define DMA0_CHAN_CTRL 0x110 124#define DMA1_CHAN_CTRL 0x130 125#define DMA2_CHAN_CTRL 0x150 126#define DMA3_CHAN_CTRL 0x170 127#define DMA4_CHAN_CTRL 0x190 128#define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan)) 129/* CHAN_CTRL registers share bits */ 130#define DMA_CHAN_CTRL_ENABLE (1<<31) 131#define DMA_CHAN_CTRL_BUSY (1<<30) 132#define DMA_CHAN_CTRL_LINK (1<<29) 133 134#define DMA0_READY 0x114 135#define DMA1_READY 0x134 136#define DMA2_READY 0x154 137#define DMA3_READY 0x174 138#define DMA4_READY 0x194 139#define DMA_READY(chan) (DMA_BREG(DMA0_READY, chan)) 140 141#define DMA_GLOBAL_REGISTER 0x908 142 143#define FIFO_SIZES 0xa00 144 145#define FIFO_CONTROL 0xa10 146#define FIFO_CONTROL_GRF_FLUSH (1<<4) 147#define FIFO_CONTROL_ITF_FLUSH (1<<3) 148#define FIFO_CONTROL_ATF_FLUSH (1<<2) 149 150#define FIFO_XMIT_THRESHOLD 0xa14 151 152#define DMA0_WORD0_CMP_VALUE 0xb00 153#define DMA1_WORD0_CMP_VALUE 0xb10 154#define DMA2_WORD0_CMP_VALUE 0xb20 155#define DMA3_WORD0_CMP_VALUE 0xb30 156#define DMA4_WORD0_CMP_VALUE 0xb40 157#define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan)) 158 159#define DMA0_WORD0_CMP_ENABLE 0xb04 160#define DMA1_WORD0_CMP_ENABLE 0xb14 161#define DMA2_WORD0_CMP_ENABLE 0xb24 162#define DMA3_WORD0_CMP_ENABLE 0xb34 163#define DMA4_WORD0_CMP_ENABLE 0xb44 164#define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE, chan)) 165 166#define DMA0_WORD1_CMP_VALUE 0xb08 167#define DMA1_WORD1_CMP_VALUE 0xb18 168#define DMA2_WORD1_CMP_VALUE 0xb28 169#define DMA3_WORD1_CMP_VALUE 0xb38 170#define DMA4_WORD1_CMP_VALUE 0xb48 171#define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan)) 172 173#define DMA0_WORD1_CMP_ENABLE 0xb0c 174#define DMA1_WORD1_CMP_ENABLE 0xb1c 175#define DMA2_WORD1_CMP_ENABLE 0xb2c 176#define DMA3_WORD1_CMP_ENABLE 0xb3c 177#define DMA4_WORD1_CMP_ENABLE 0xb4c 178#define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE, chan)) 179/* word 1 compare enable flags */ 180#define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15) 181#define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14) 182#define DMA_WORD1_CMP_MATCH_BUS_BCAST (1<<13) 183#define DMA_WORD1_CMP_MATCH_LOCAL_NODE (1<<12) 184#define DMA_WORD1_CMP_MATCH_EXACT (1<<11) 185#define DMA_WORD1_CMP_ENABLE_SELF_ID (1<<10) 186#define DMA_WORD1_CMP_ENABLE_MASTER (1<<8) 187 188#define LINK_ID 0xf00 189#define LINK_ID_BUS(id) (id<<22) 190#define LINK_ID_NODE(id) (id<<16) 191 192#define LINK_CONTROL 0xf04 193#define LINK_CONTROL_BUSY (1<<29) 194#define LINK_CONTROL_TX_ISO_EN (1<<26) 195#define LINK_CONTROL_RX_ISO_EN (1<<25) 196#define LINK_CONTROL_TX_ASYNC_EN (1<<24) 197#define LINK_CONTROL_RX_ASYNC_EN (1<<23) 198#define LINK_CONTROL_RESET_TX (1<<21) 199#define LINK_CONTROL_RESET_RX (1<<20) 200#define LINK_CONTROL_CYCMASTER (1<<11) 201#define LINK_CONTROL_CYCSOURCE (1<<10) 202#define LINK_CONTROL_CYCTIMEREN (1<<9) 203#define LINK_CONTROL_RCV_CMP_VALID (1<<7) 204#define LINK_CONTROL_SNOOP_ENABLE (1<<6) 205 206#define CYCLE_TIMER 0xf08 207 208#define LINK_PHY 0xf0c 209#define LINK_PHY_READ (1<<31) 210#define LINK_PHY_WRITE (1<<30) 211#define LINK_PHY_ADDR(addr) (addr<<24) 212#define LINK_PHY_WDATA(data) (data<<16) 213#define LINK_PHY_RADDR(addr) (addr<<8) 214 215#define LINK_INT_STATUS 0xf14 216#define LINK_INT_ENABLE 0xf18 217/* status and enable have identical bit numbers */ 218#define LINK_INT_LINK_INT (1<<31) 219#define LINK_INT_PHY_TIME_OUT (1<<30) 220#define LINK_INT_PHY_REG_RCVD (1<<29) 221#define LINK_INT_PHY_BUSRESET (1<<28) 222#define LINK_INT_TX_RDY (1<<26) 223#define LINK_INT_RX_DATA_RDY (1<<25) 224#define LINK_INT_IT_STUCK (1<<20) 225#define LINK_INT_AT_STUCK (1<<19) 226#define LINK_INT_SNTRJ (1<<17) 227#define LINK_INT_HDR_ERR (1<<16) 228#define LINK_INT_TC_ERR (1<<15) 229#define LINK_INT_CYC_SEC (1<<11) 230#define LINK_INT_CYC_STRT (1<<10) 231#define LINK_INT_CYC_DONE (1<<9) 232#define LINK_INT_CYC_PEND (1<<8) 233#define LINK_INT_CYC_LOST (1<<7) 234#define LINK_INT_CYC_ARB_FAILED (1<<6) 235#define LINK_INT_GRF_OVER_FLOW (1<<5) 236#define LINK_INT_ITF_UNDER_FLOW (1<<4) 237#define LINK_INT_ATF_UNDER_FLOW (1<<3) 238#define LINK_INT_IARB_FAILED (1<<0)