cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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altera-fpga2sdram.c (5011B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
      4 *
      5 *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
      6 */
      7
      8/*
      9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
     10 * host processor system (HPS).
     11 *
     12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
     13 * Reconfiguring these ports requires that no SDRAM transactions occur during
     14 * reconfiguration.  The code reconfiguring the ports cannot run out of SDRAM
     15 * nor can the FPGA access the SDRAM during reconfiguration.  This driver does
     16 * not support reconfiguring the ports.  The ports are configured by code
     17 * running out of on chip ram before Linux is started and the configuration
     18 * is passed in a handoff register in the system manager.
     19 *
     20 * This driver supports enabling and disabling of the configured ports, which
     21 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
     22 * uses the same port configuration.  Bridges must be disabled before
     23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
     24 */
     25
     26#include <linux/fpga/fpga-bridge.h>
     27#include <linux/kernel.h>
     28#include <linux/mfd/syscon.h>
     29#include <linux/module.h>
     30#include <linux/of_platform.h>
     31#include <linux/regmap.h>
     32
     33#define ALT_SDR_CTL_FPGAPORTRST_OFST		0x80
     34#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK	0x00003fff
     35#define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT	0
     36#define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT	4
     37#define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT	8
     38
     39/*
     40 * From the Cyclone V HPS Memory Map document:
     41 *   These registers are used to store handoff information between the
     42 *   preloader and the OS. These 8 registers can be used to store any
     43 *   information. The contents of these registers have no impact on
     44 *   the state of the HPS hardware.
     45 */
     46#define SYSMGR_ISWGRP_HANDOFF3          (0x8C)
     47
     48#define F2S_BRIDGE_NAME "fpga2sdram"
     49
     50struct alt_fpga2sdram_data {
     51	struct device *dev;
     52	struct regmap *sdrctl;
     53	int mask;
     54};
     55
     56static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge)
     57{
     58	struct alt_fpga2sdram_data *priv = bridge->priv;
     59	int value;
     60
     61	regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value);
     62
     63	return (value & priv->mask) == priv->mask;
     64}
     65
     66static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv,
     67					     bool enable)
     68{
     69	return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST,
     70				  priv->mask, enable ? priv->mask : 0);
     71}
     72
     73static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable)
     74{
     75	return _alt_fpga2sdram_enable_set(bridge->priv, enable);
     76}
     77
     78struct prop_map {
     79	char *prop_name;
     80	u32 *prop_value;
     81	u32 prop_max;
     82};
     83
     84static const struct fpga_bridge_ops altera_fpga2sdram_br_ops = {
     85	.enable_set = alt_fpga2sdram_enable_set,
     86	.enable_show = alt_fpga2sdram_enable_show,
     87};
     88
     89static const struct of_device_id altera_fpga_of_match[] = {
     90	{ .compatible = "altr,socfpga-fpga2sdram-bridge" },
     91	{},
     92};
     93
     94static int alt_fpga_bridge_probe(struct platform_device *pdev)
     95{
     96	struct device *dev = &pdev->dev;
     97	struct alt_fpga2sdram_data *priv;
     98	struct fpga_bridge *br;
     99	u32 enable;
    100	struct regmap *sysmgr;
    101	int ret = 0;
    102
    103	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
    104	if (!priv)
    105		return -ENOMEM;
    106
    107	priv->dev = dev;
    108
    109	priv->sdrctl = syscon_regmap_lookup_by_compatible("altr,sdr-ctl");
    110	if (IS_ERR(priv->sdrctl)) {
    111		dev_err(dev, "regmap for altr,sdr-ctl lookup failed.\n");
    112		return PTR_ERR(priv->sdrctl);
    113	}
    114
    115	sysmgr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
    116	if (IS_ERR(sysmgr)) {
    117		dev_err(dev, "regmap for altr,sys-mgr lookup failed.\n");
    118		return PTR_ERR(sysmgr);
    119	}
    120
    121	/* Get f2s bridge configuration saved in handoff register */
    122	regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask);
    123
    124	br = fpga_bridge_register(dev, F2S_BRIDGE_NAME,
    125				  &altera_fpga2sdram_br_ops, priv);
    126	if (IS_ERR(br))
    127		return PTR_ERR(br);
    128
    129	platform_set_drvdata(pdev, br);
    130
    131	dev_info(dev, "driver initialized with handoff %08x\n", priv->mask);
    132
    133	if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
    134		if (enable > 1) {
    135			dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
    136		} else {
    137			dev_info(dev, "%s bridge\n",
    138				 (enable ? "enabling" : "disabling"));
    139			ret = _alt_fpga2sdram_enable_set(priv, enable);
    140			if (ret) {
    141				fpga_bridge_unregister(br);
    142				return ret;
    143			}
    144		}
    145	}
    146
    147	return ret;
    148}
    149
    150static int alt_fpga_bridge_remove(struct platform_device *pdev)
    151{
    152	struct fpga_bridge *br = platform_get_drvdata(pdev);
    153
    154	fpga_bridge_unregister(br);
    155
    156	return 0;
    157}
    158
    159MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
    160
    161static struct platform_driver altera_fpga_driver = {
    162	.probe = alt_fpga_bridge_probe,
    163	.remove = alt_fpga_bridge_remove,
    164	.driver = {
    165		.name	= "altera_fpga2sdram_bridge",
    166		.of_match_table = of_match_ptr(altera_fpga_of_match),
    167	},
    168};
    169
    170module_platform_driver(altera_fpga_driver);
    171
    172MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
    173MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
    174MODULE_LICENSE("GPL v2");