cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dfl-fme-pr.h (2091B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
      4 *
      5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
      6 *
      7 * Authors:
      8 *   Kang Luwei <luwei.kang@intel.com>
      9 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
     10 *   Wu Hao <hao.wu@intel.com>
     11 *   Joseph Grecco <joe.grecco@intel.com>
     12 *   Enno Luebbers <enno.luebbers@intel.com>
     13 *   Tim Whisonant <tim.whisonant@intel.com>
     14 *   Ananda Ravuri <ananda.ravuri@intel.com>
     15 *   Henry Mitchel <henry.mitchel@intel.com>
     16 */
     17
     18#ifndef __DFL_FME_PR_H
     19#define __DFL_FME_PR_H
     20
     21#include <linux/platform_device.h>
     22
     23/**
     24 * struct dfl_fme_region - FME fpga region data structure
     25 *
     26 * @region: platform device of the FPGA region.
     27 * @node: used to link fme_region to a list.
     28 * @port_id: indicate which port this region connected to.
     29 */
     30struct dfl_fme_region {
     31	struct platform_device *region;
     32	struct list_head node;
     33	int port_id;
     34};
     35
     36/**
     37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
     38 *
     39 * @mgr: platform device of the FPGA manager.
     40 * @br: platform device of the FPGA bridge.
     41 * @region_id: region id (same as port_id).
     42 */
     43struct dfl_fme_region_pdata {
     44	struct platform_device *mgr;
     45	struct platform_device *br;
     46	int region_id;
     47};
     48
     49/**
     50 * struct dfl_fme_bridge - FME fpga bridge data structure
     51 *
     52 * @br: platform device of the FPGA bridge.
     53 * @node: used to link fme_bridge to a list.
     54 */
     55struct dfl_fme_bridge {
     56	struct platform_device *br;
     57	struct list_head node;
     58};
     59
     60/**
     61 * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
     62 *
     63 * @cdev: container device.
     64 * @port_id: port id.
     65 */
     66struct dfl_fme_br_pdata {
     67	struct dfl_fpga_cdev *cdev;
     68	int port_id;
     69};
     70
     71/**
     72 * struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
     73 *
     74 * @ioaddr: mapped io address for FME manager platform device.
     75 */
     76struct dfl_fme_mgr_pdata {
     77	void __iomem *ioaddr;
     78};
     79
     80#define DFL_FPGA_FME_MGR	"dfl-fme-mgr"
     81#define DFL_FPGA_FME_BRIDGE	"dfl-fme-bridge"
     82#define DFL_FPGA_FME_REGION	"dfl-fme-region"
     83
     84#endif /* __DFL_FME_PR_H */