dfl-fme-region.c (2124B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * FPGA Region Driver for FPGA Management Engine (FME) 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Wu Hao <hao.wu@intel.com> 9 * Joseph Grecco <joe.grecco@intel.com> 10 * Enno Luebbers <enno.luebbers@intel.com> 11 * Tim Whisonant <tim.whisonant@intel.com> 12 * Ananda Ravuri <ananda.ravuri@intel.com> 13 * Henry Mitchel <henry.mitchel@intel.com> 14 */ 15 16#include <linux/module.h> 17#include <linux/fpga/fpga-mgr.h> 18#include <linux/fpga/fpga-region.h> 19 20#include "dfl-fme-pr.h" 21 22static int fme_region_get_bridges(struct fpga_region *region) 23{ 24 struct dfl_fme_region_pdata *pdata = region->priv; 25 struct device *dev = &pdata->br->dev; 26 27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); 28} 29 30static int fme_region_probe(struct platform_device *pdev) 31{ 32 struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev); 33 struct fpga_region_info info = { 0 }; 34 struct device *dev = &pdev->dev; 35 struct fpga_region *region; 36 struct fpga_manager *mgr; 37 int ret; 38 39 mgr = fpga_mgr_get(&pdata->mgr->dev); 40 if (IS_ERR(mgr)) 41 return -EPROBE_DEFER; 42 43 info.mgr = mgr; 44 info.compat_id = mgr->compat_id; 45 info.get_bridges = fme_region_get_bridges; 46 info.priv = pdata; 47 region = fpga_region_register_full(dev, &info); 48 if (IS_ERR(region)) { 49 ret = PTR_ERR(region); 50 goto eprobe_mgr_put; 51 } 52 53 platform_set_drvdata(pdev, region); 54 55 dev_dbg(dev, "DFL FME FPGA Region probed\n"); 56 57 return 0; 58 59eprobe_mgr_put: 60 fpga_mgr_put(mgr); 61 return ret; 62} 63 64static int fme_region_remove(struct platform_device *pdev) 65{ 66 struct fpga_region *region = platform_get_drvdata(pdev); 67 struct fpga_manager *mgr = region->mgr; 68 69 fpga_region_unregister(region); 70 fpga_mgr_put(mgr); 71 72 return 0; 73} 74 75static struct platform_driver fme_region_driver = { 76 .driver = { 77 .name = DFL_FPGA_FME_REGION, 78 }, 79 .probe = fme_region_probe, 80 .remove = fme_region_remove, 81}; 82 83module_platform_driver(fme_region_driver); 84 85MODULE_DESCRIPTION("FPGA Region for DFL FPGA Management Engine"); 86MODULE_AUTHOR("Intel Corporation"); 87MODULE_LICENSE("GPL v2"); 88MODULE_ALIAS("platform:dfl-fme-region");