cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpio-sta2x11.c (10680B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * STMicroelectronics ConneXt (STA2X11) GPIO driver
      4 *
      5 * Copyright 2012 ST Microelectronics (Alessandro Rubini)
      6 * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
      7 * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
      8 */
      9
     10#include <linux/init.h>
     11#include <linux/kernel.h>
     12#include <linux/slab.h>
     13#include <linux/gpio/driver.h>
     14#include <linux/bitops.h>
     15#include <linux/interrupt.h>
     16#include <linux/irq.h>
     17#include <linux/pci.h>
     18#include <linux/platform_device.h>
     19#include <linux/mfd/sta2x11-mfd.h>
     20
     21struct gsta_regs {
     22	u32 dat;		/* 0x00 */
     23	u32 dats;
     24	u32 datc;
     25	u32 pdis;
     26	u32 dir;		/* 0x10 */
     27	u32 dirs;
     28	u32 dirc;
     29	u32 unused_1c;
     30	u32 afsela;		/* 0x20 */
     31	u32 unused_24[7];
     32	u32 rimsc;		/* 0x40 */
     33	u32 fimsc;
     34	u32 is;
     35	u32 ic;
     36};
     37
     38struct gsta_gpio {
     39	spinlock_t			lock;
     40	struct device			*dev;
     41	void __iomem			*reg_base;
     42	struct gsta_regs __iomem	*regs[GSTA_NR_BLOCKS];
     43	struct gpio_chip		gpio;
     44	int				irq_base;
     45	/* FIXME: save the whole config here (AF, ...) */
     46	unsigned			irq_type[GSTA_NR_GPIO];
     47};
     48
     49/*
     50 * gpio methods
     51 */
     52
     53static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
     54{
     55	struct gsta_gpio *chip = gpiochip_get_data(gpio);
     56	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
     57	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
     58
     59	if (val)
     60		writel(bit, &regs->dats);
     61	else
     62		writel(bit, &regs->datc);
     63}
     64
     65static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
     66{
     67	struct gsta_gpio *chip = gpiochip_get_data(gpio);
     68	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
     69	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
     70
     71	return !!(readl(&regs->dat) & bit);
     72}
     73
     74static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
     75				      int val)
     76{
     77	struct gsta_gpio *chip = gpiochip_get_data(gpio);
     78	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
     79	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
     80
     81	writel(bit, &regs->dirs);
     82	/* Data register after direction, otherwise pullup/down is selected */
     83	if (val)
     84		writel(bit, &regs->dats);
     85	else
     86		writel(bit, &regs->datc);
     87	return 0;
     88}
     89
     90static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
     91{
     92	struct gsta_gpio *chip = gpiochip_get_data(gpio);
     93	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
     94	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
     95
     96	writel(bit, &regs->dirc);
     97	return 0;
     98}
     99
    100static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
    101{
    102	struct gsta_gpio *chip = gpiochip_get_data(gpio);
    103	return chip->irq_base + offset;
    104}
    105
    106static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
    107{
    108	struct gpio_chip *gpio = &chip->gpio;
    109
    110	/*
    111	 * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
    112	 * from the end. However, for compatibility, we need the first
    113	 * ConneXt device to start from gpio 0: it's the main chipset
    114	 * on most boards so documents and drivers assume gpio0..gpio127
    115	 */
    116	static int gpio_base;
    117
    118	gpio->label = dev_name(chip->dev);
    119	gpio->owner = THIS_MODULE;
    120	gpio->direction_input = gsta_gpio_direction_input;
    121	gpio->get = gsta_gpio_get;
    122	gpio->direction_output = gsta_gpio_direction_output;
    123	gpio->set = gsta_gpio_set;
    124	gpio->dbg_show = NULL;
    125	gpio->base = gpio_base;
    126	gpio->ngpio = GSTA_NR_GPIO;
    127	gpio->can_sleep = false;
    128	gpio->to_irq = gsta_gpio_to_irq;
    129
    130	/*
    131	 * After the first device, turn to dynamic gpio numbers.
    132	 * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
    133	 */
    134	if (!gpio_base)
    135		gpio_base = -1;
    136}
    137
    138/*
    139 * Special method: alternate functions and pullup/pulldown. This is only
    140 * invoked on startup to configure gpio's according to platform data.
    141 * FIXME : this functionality shall be managed (and exported to other drivers)
    142 * via the pin control subsystem.
    143 */
    144static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
    145{
    146	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
    147	unsigned long flags;
    148	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
    149	u32 val;
    150	int err = 0;
    151
    152	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
    153
    154	if (cfg == PINMUX_TYPE_NONE)
    155		return;
    156
    157	/* Alternate function or not? */
    158	spin_lock_irqsave(&chip->lock, flags);
    159	val = readl(&regs->afsela);
    160	if (cfg == PINMUX_TYPE_FUNCTION)
    161		val |= bit;
    162	else
    163		val &= ~bit;
    164	writel(val | bit, &regs->afsela);
    165	if (cfg == PINMUX_TYPE_FUNCTION) {
    166		spin_unlock_irqrestore(&chip->lock, flags);
    167		return;
    168	}
    169
    170	/* not alternate function: set details */
    171	switch (cfg) {
    172	case PINMUX_TYPE_OUTPUT_LOW:
    173		writel(bit, &regs->dirs);
    174		writel(bit, &regs->datc);
    175		break;
    176	case PINMUX_TYPE_OUTPUT_HIGH:
    177		writel(bit, &regs->dirs);
    178		writel(bit, &regs->dats);
    179		break;
    180	case PINMUX_TYPE_INPUT:
    181		writel(bit, &regs->dirc);
    182		val = readl(&regs->pdis) | bit;
    183		writel(val, &regs->pdis);
    184		break;
    185	case PINMUX_TYPE_INPUT_PULLUP:
    186		writel(bit, &regs->dirc);
    187		val = readl(&regs->pdis) & ~bit;
    188		writel(val, &regs->pdis);
    189		writel(bit, &regs->dats);
    190		break;
    191	case PINMUX_TYPE_INPUT_PULLDOWN:
    192		writel(bit, &regs->dirc);
    193		val = readl(&regs->pdis) & ~bit;
    194		writel(val, &regs->pdis);
    195		writel(bit, &regs->datc);
    196		break;
    197	default:
    198		err = 1;
    199	}
    200	spin_unlock_irqrestore(&chip->lock, flags);
    201	if (err)
    202		pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
    203		       __func__, chip, nr, cfg);
    204}
    205
    206/*
    207 * Irq methods
    208 */
    209
    210static void gsta_irq_disable(struct irq_data *data)
    211{
    212	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
    213	struct gsta_gpio *chip = gc->private;
    214	int nr = data->irq - chip->irq_base;
    215	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
    216	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
    217	u32 val;
    218	unsigned long flags;
    219
    220	spin_lock_irqsave(&chip->lock, flags);
    221	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
    222		val = readl(&regs->rimsc) & ~bit;
    223		writel(val, &regs->rimsc);
    224	}
    225	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
    226		val = readl(&regs->fimsc) & ~bit;
    227		writel(val, &regs->fimsc);
    228	}
    229	spin_unlock_irqrestore(&chip->lock, flags);
    230	return;
    231}
    232
    233static void gsta_irq_enable(struct irq_data *data)
    234{
    235	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
    236	struct gsta_gpio *chip = gc->private;
    237	int nr = data->irq - chip->irq_base;
    238	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
    239	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
    240	u32 val;
    241	int type;
    242	unsigned long flags;
    243
    244	type = chip->irq_type[nr];
    245
    246	spin_lock_irqsave(&chip->lock, flags);
    247	val = readl(&regs->rimsc);
    248	if (type & IRQ_TYPE_EDGE_RISING)
    249		writel(val | bit, &regs->rimsc);
    250	else
    251		writel(val & ~bit, &regs->rimsc);
    252	val = readl(&regs->rimsc);
    253	if (type & IRQ_TYPE_EDGE_FALLING)
    254		writel(val | bit, &regs->fimsc);
    255	else
    256		writel(val & ~bit, &regs->fimsc);
    257	spin_unlock_irqrestore(&chip->lock, flags);
    258	return;
    259}
    260
    261static int gsta_irq_type(struct irq_data *d, unsigned int type)
    262{
    263	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
    264	struct gsta_gpio *chip = gc->private;
    265	int nr = d->irq - chip->irq_base;
    266
    267	/* We only support edge interrupts */
    268	if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
    269		pr_debug("%s: unsupported type 0x%x\n", __func__, type);
    270		return -EINVAL;
    271	}
    272
    273	chip->irq_type[nr] = type; /* used for enable/disable */
    274
    275	gsta_irq_enable(d);
    276	return 0;
    277}
    278
    279static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
    280{
    281	struct gsta_gpio *chip = dev_id;
    282	struct gsta_regs __iomem *regs;
    283	u32 is;
    284	int i, nr, base;
    285	irqreturn_t ret = IRQ_NONE;
    286
    287	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
    288		regs = chip->regs[i];
    289		base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
    290		while ((is = readl(&regs->is))) {
    291			nr = __ffs(is);
    292			irq = base + nr;
    293			generic_handle_irq(irq);
    294			writel(1 << nr, &regs->ic);
    295			ret = IRQ_HANDLED;
    296		}
    297	}
    298	return ret;
    299}
    300
    301static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
    302{
    303	struct irq_chip_generic *gc;
    304	struct irq_chip_type *ct;
    305	int rv;
    306
    307	gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
    308					 chip->irq_base,
    309					 chip->reg_base, handle_simple_irq);
    310	if (!gc)
    311		return -ENOMEM;
    312
    313	gc->private = chip;
    314	ct = gc->chip_types;
    315
    316	ct->chip.irq_set_type = gsta_irq_type;
    317	ct->chip.irq_disable = gsta_irq_disable;
    318	ct->chip.irq_enable = gsta_irq_enable;
    319
    320	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
    321	rv = devm_irq_setup_generic_chip(chip->dev, gc,
    322					 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
    323					 0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
    324	if (rv)
    325		return rv;
    326
    327	/* Set up all 128 interrupts: code from setup_generic_chip */
    328	{
    329		struct irq_chip_type *ct = gc->chip_types;
    330		int i, j;
    331		for (j = 0; j < GSTA_NR_GPIO; j++) {
    332			i = chip->irq_base + j;
    333			irq_set_chip_and_handler(i, &ct->chip, ct->handler);
    334			irq_set_chip_data(i, gc);
    335			irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
    336		}
    337		gc->irq_cnt = i - gc->irq_base;
    338	}
    339
    340	return 0;
    341}
    342
    343/* The platform device used here is instantiated by the MFD device */
    344static int gsta_probe(struct platform_device *dev)
    345{
    346	int i, err;
    347	struct pci_dev *pdev;
    348	struct sta2x11_gpio_pdata *gpio_pdata;
    349	struct gsta_gpio *chip;
    350
    351	pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
    352	gpio_pdata = dev_get_platdata(&pdev->dev);
    353
    354	if (gpio_pdata == NULL)
    355		dev_err(&dev->dev, "no gpio config\n");
    356	pr_debug("gpio config: %p\n", gpio_pdata);
    357
    358	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
    359	if (!chip)
    360		return -ENOMEM;
    361	chip->dev = &dev->dev;
    362	chip->reg_base = devm_platform_ioremap_resource(dev, 0);
    363	if (IS_ERR(chip->reg_base))
    364		return PTR_ERR(chip->reg_base);
    365
    366	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
    367		chip->regs[i] = chip->reg_base + i * 4096;
    368		/* disable all irqs */
    369		writel(0, &chip->regs[i]->rimsc);
    370		writel(0, &chip->regs[i]->fimsc);
    371		writel(~0, &chip->regs[i]->ic);
    372	}
    373	spin_lock_init(&chip->lock);
    374	gsta_gpio_setup(chip);
    375	if (gpio_pdata)
    376		for (i = 0; i < GSTA_NR_GPIO; i++)
    377			gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
    378
    379	/* 384 was used in previous code: be compatible for other drivers */
    380	err = devm_irq_alloc_descs(&dev->dev, -1, 384,
    381				   GSTA_NR_GPIO, NUMA_NO_NODE);
    382	if (err < 0) {
    383		dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
    384			 -err);
    385		return err;
    386	}
    387	chip->irq_base = err;
    388
    389	err = gsta_alloc_irq_chip(chip);
    390	if (err)
    391		return err;
    392
    393	err = devm_request_irq(&dev->dev, pdev->irq, gsta_gpio_handler,
    394			       IRQF_SHARED, KBUILD_MODNAME, chip);
    395	if (err < 0) {
    396		dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
    397			-err);
    398		return err;
    399	}
    400
    401	return devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
    402}
    403
    404static struct platform_driver sta2x11_gpio_platform_driver = {
    405	.driver = {
    406		.name	= "sta2x11-gpio",
    407		.suppress_bind_attrs = true,
    408	},
    409	.probe = gsta_probe,
    410};
    411builtin_platform_driver(sta2x11_gpio_platform_driver);