cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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amdgpu.h (44844B)


      1/*
      2 * Copyright 2008 Advanced Micro Devices, Inc.
      3 * Copyright 2008 Red Hat Inc.
      4 * Copyright 2009 Jerome Glisse.
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a
      7 * copy of this software and associated documentation files (the "Software"),
      8 * to deal in the Software without restriction, including without limitation
      9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10 * and/or sell copies of the Software, and to permit persons to whom the
     11 * Software is furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22 * OTHER DEALINGS IN THE SOFTWARE.
     23 *
     24 * Authors: Dave Airlie
     25 *          Alex Deucher
     26 *          Jerome Glisse
     27 */
     28#ifndef __AMDGPU_H__
     29#define __AMDGPU_H__
     30
     31#ifdef pr_fmt
     32#undef pr_fmt
     33#endif
     34
     35#define pr_fmt(fmt) "amdgpu: " fmt
     36
     37#ifdef dev_fmt
     38#undef dev_fmt
     39#endif
     40
     41#define dev_fmt(fmt) "amdgpu: " fmt
     42
     43#include "amdgpu_ctx.h"
     44
     45#include <linux/atomic.h>
     46#include <linux/wait.h>
     47#include <linux/list.h>
     48#include <linux/kref.h>
     49#include <linux/rbtree.h>
     50#include <linux/hashtable.h>
     51#include <linux/dma-fence.h>
     52#include <linux/pci.h>
     53#include <linux/aer.h>
     54
     55#include <drm/ttm/ttm_bo_api.h>
     56#include <drm/ttm/ttm_bo_driver.h>
     57#include <drm/ttm/ttm_placement.h>
     58#include <drm/ttm/ttm_execbuf_util.h>
     59
     60#include <drm/amdgpu_drm.h>
     61#include <drm/drm_gem.h>
     62#include <drm/drm_ioctl.h>
     63
     64#include <kgd_kfd_interface.h>
     65#include "dm_pp_interface.h"
     66#include "kgd_pp_interface.h"
     67
     68#include "amd_shared.h"
     69#include "amdgpu_mode.h"
     70#include "amdgpu_ih.h"
     71#include "amdgpu_irq.h"
     72#include "amdgpu_ucode.h"
     73#include "amdgpu_ttm.h"
     74#include "amdgpu_psp.h"
     75#include "amdgpu_gds.h"
     76#include "amdgpu_sync.h"
     77#include "amdgpu_ring.h"
     78#include "amdgpu_vm.h"
     79#include "amdgpu_dpm.h"
     80#include "amdgpu_acp.h"
     81#include "amdgpu_uvd.h"
     82#include "amdgpu_vce.h"
     83#include "amdgpu_vcn.h"
     84#include "amdgpu_jpeg.h"
     85#include "amdgpu_mn.h"
     86#include "amdgpu_gmc.h"
     87#include "amdgpu_gfx.h"
     88#include "amdgpu_sdma.h"
     89#include "amdgpu_lsdma.h"
     90#include "amdgpu_nbio.h"
     91#include "amdgpu_hdp.h"
     92#include "amdgpu_dm.h"
     93#include "amdgpu_virt.h"
     94#include "amdgpu_csa.h"
     95#include "amdgpu_mes_ctx.h"
     96#include "amdgpu_gart.h"
     97#include "amdgpu_debugfs.h"
     98#include "amdgpu_job.h"
     99#include "amdgpu_bo_list.h"
    100#include "amdgpu_gem.h"
    101#include "amdgpu_doorbell.h"
    102#include "amdgpu_amdkfd.h"
    103#include "amdgpu_discovery.h"
    104#include "amdgpu_mes.h"
    105#include "amdgpu_umc.h"
    106#include "amdgpu_mmhub.h"
    107#include "amdgpu_gfxhub.h"
    108#include "amdgpu_df.h"
    109#include "amdgpu_smuio.h"
    110#include "amdgpu_fdinfo.h"
    111#include "amdgpu_mca.h"
    112#include "amdgpu_ras.h"
    113
    114#define MAX_GPU_INSTANCE		16
    115
    116struct amdgpu_gpu_instance
    117{
    118	struct amdgpu_device		*adev;
    119	int				mgpu_fan_enabled;
    120};
    121
    122struct amdgpu_mgpu_info
    123{
    124	struct amdgpu_gpu_instance	gpu_ins[MAX_GPU_INSTANCE];
    125	struct mutex			mutex;
    126	uint32_t			num_gpu;
    127	uint32_t			num_dgpu;
    128	uint32_t			num_apu;
    129
    130	/* delayed reset_func for XGMI configuration if necessary */
    131	struct delayed_work		delayed_reset_work;
    132	bool				pending_reset;
    133};
    134
    135enum amdgpu_ss {
    136	AMDGPU_SS_DRV_LOAD,
    137	AMDGPU_SS_DEV_D0,
    138	AMDGPU_SS_DEV_D3,
    139	AMDGPU_SS_DRV_UNLOAD
    140};
    141
    142struct amdgpu_watchdog_timer
    143{
    144	bool timeout_fatal_disable;
    145	uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
    146};
    147
    148#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256
    149
    150/*
    151 * Modules parameters.
    152 */
    153extern int amdgpu_modeset;
    154extern int amdgpu_vram_limit;
    155extern int amdgpu_vis_vram_limit;
    156extern int amdgpu_gart_size;
    157extern int amdgpu_gtt_size;
    158extern int amdgpu_moverate;
    159extern int amdgpu_audio;
    160extern int amdgpu_disp_priority;
    161extern int amdgpu_hw_i2c;
    162extern int amdgpu_pcie_gen2;
    163extern int amdgpu_msi;
    164extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
    165extern int amdgpu_dpm;
    166extern int amdgpu_fw_load_type;
    167extern int amdgpu_aspm;
    168extern int amdgpu_runtime_pm;
    169extern uint amdgpu_ip_block_mask;
    170extern int amdgpu_bapm;
    171extern int amdgpu_deep_color;
    172extern int amdgpu_vm_size;
    173extern int amdgpu_vm_block_size;
    174extern int amdgpu_vm_fragment_size;
    175extern int amdgpu_vm_fault_stop;
    176extern int amdgpu_vm_debug;
    177extern int amdgpu_vm_update_mode;
    178extern int amdgpu_exp_hw_support;
    179extern int amdgpu_dc;
    180extern int amdgpu_sched_jobs;
    181extern int amdgpu_sched_hw_submission;
    182extern uint amdgpu_pcie_gen_cap;
    183extern uint amdgpu_pcie_lane_cap;
    184extern u64 amdgpu_cg_mask;
    185extern uint amdgpu_pg_mask;
    186extern uint amdgpu_sdma_phase_quantum;
    187extern char *amdgpu_disable_cu;
    188extern char *amdgpu_virtual_display;
    189extern uint amdgpu_pp_feature_mask;
    190extern uint amdgpu_force_long_training;
    191extern int amdgpu_job_hang_limit;
    192extern int amdgpu_lbpw;
    193extern int amdgpu_compute_multipipe;
    194extern int amdgpu_gpu_recovery;
    195extern int amdgpu_emu_mode;
    196extern uint amdgpu_smu_memory_pool_size;
    197extern int amdgpu_smu_pptable_id;
    198extern uint amdgpu_dc_feature_mask;
    199extern uint amdgpu_dc_debug_mask;
    200extern uint amdgpu_dm_abm_level;
    201extern int amdgpu_backlight;
    202extern struct amdgpu_mgpu_info mgpu_info;
    203extern int amdgpu_ras_enable;
    204extern uint amdgpu_ras_mask;
    205extern int amdgpu_bad_page_threshold;
    206extern bool amdgpu_ignore_bad_page_threshold;
    207extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
    208extern int amdgpu_async_gfx_ring;
    209extern int amdgpu_mcbp;
    210extern int amdgpu_discovery;
    211extern int amdgpu_mes;
    212extern int amdgpu_mes_kiq;
    213extern int amdgpu_noretry;
    214extern int amdgpu_force_asic_type;
    215extern int amdgpu_smartshift_bias;
    216extern int amdgpu_use_xgmi_p2p;
    217#ifdef CONFIG_HSA_AMD
    218extern int sched_policy;
    219extern bool debug_evictions;
    220extern bool no_system_mem_limit;
    221#else
    222static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
    223static const bool __maybe_unused debug_evictions; /* = false */
    224static const bool __maybe_unused no_system_mem_limit;
    225#endif
    226
    227extern int amdgpu_tmz;
    228extern int amdgpu_reset_method;
    229
    230#ifdef CONFIG_DRM_AMDGPU_SI
    231extern int amdgpu_si_support;
    232#endif
    233#ifdef CONFIG_DRM_AMDGPU_CIK
    234extern int amdgpu_cik_support;
    235#endif
    236extern int amdgpu_num_kcq;
    237
    238#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
    239extern int amdgpu_vcnfw_log;
    240
    241#define AMDGPU_VM_MAX_NUM_CTX			4096
    242#define AMDGPU_SG_THRESHOLD			(256*1024*1024)
    243#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */
    244#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
    245#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
    246#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
    247#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
    248#define AMDGPUFB_CONN_LIMIT			4
    249#define AMDGPU_BIOS_NUM_SCRATCH			16
    250
    251#define AMDGPU_VBIOS_VGA_ALLOCATION		(9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
    252
    253/* hard reset data */
    254#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
    255
    256/* reset flags */
    257#define AMDGPU_RESET_GFX			(1 << 0)
    258#define AMDGPU_RESET_COMPUTE			(1 << 1)
    259#define AMDGPU_RESET_DMA			(1 << 2)
    260#define AMDGPU_RESET_CP				(1 << 3)
    261#define AMDGPU_RESET_GRBM			(1 << 4)
    262#define AMDGPU_RESET_DMA1			(1 << 5)
    263#define AMDGPU_RESET_RLC			(1 << 6)
    264#define AMDGPU_RESET_SEM			(1 << 7)
    265#define AMDGPU_RESET_IH				(1 << 8)
    266#define AMDGPU_RESET_VMC			(1 << 9)
    267#define AMDGPU_RESET_MC				(1 << 10)
    268#define AMDGPU_RESET_DISPLAY			(1 << 11)
    269#define AMDGPU_RESET_UVD			(1 << 12)
    270#define AMDGPU_RESET_VCE			(1 << 13)
    271#define AMDGPU_RESET_VCE1			(1 << 14)
    272
    273/* max cursor sizes (in pixels) */
    274#define CIK_CURSOR_WIDTH 128
    275#define CIK_CURSOR_HEIGHT 128
    276
    277/* smasrt shift bias level limits */
    278#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
    279#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
    280
    281struct amdgpu_device;
    282struct amdgpu_irq_src;
    283struct amdgpu_fpriv;
    284struct amdgpu_bo_va_mapping;
    285struct kfd_vm_fault_info;
    286struct amdgpu_hive_info;
    287struct amdgpu_reset_context;
    288struct amdgpu_reset_control;
    289
    290enum amdgpu_cp_irq {
    291	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
    292	AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
    293	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
    294	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
    295	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
    296	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
    297	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
    298	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
    299	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
    300	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
    301
    302	AMDGPU_CP_IRQ_LAST
    303};
    304
    305enum amdgpu_thermal_irq {
    306	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
    307	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
    308
    309	AMDGPU_THERMAL_IRQ_LAST
    310};
    311
    312enum amdgpu_kiq_irq {
    313	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
    314	AMDGPU_CP_KIQ_IRQ_LAST
    315};
    316
    317#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
    318#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
    319#define MAX_KIQ_REG_TRY 1000
    320
    321int amdgpu_device_ip_set_clockgating_state(void *dev,
    322					   enum amd_ip_block_type block_type,
    323					   enum amd_clockgating_state state);
    324int amdgpu_device_ip_set_powergating_state(void *dev,
    325					   enum amd_ip_block_type block_type,
    326					   enum amd_powergating_state state);
    327void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
    328					    u64 *flags);
    329int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
    330				   enum amd_ip_block_type block_type);
    331bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
    332			      enum amd_ip_block_type block_type);
    333
    334#define AMDGPU_MAX_IP_NUM 16
    335
    336struct amdgpu_ip_block_status {
    337	bool valid;
    338	bool sw;
    339	bool hw;
    340	bool late_initialized;
    341	bool hang;
    342};
    343
    344struct amdgpu_ip_block_version {
    345	const enum amd_ip_block_type type;
    346	const u32 major;
    347	const u32 minor;
    348	const u32 rev;
    349	const struct amd_ip_funcs *funcs;
    350};
    351
    352#define HW_REV(_Major, _Minor, _Rev) \
    353	((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
    354
    355struct amdgpu_ip_block {
    356	struct amdgpu_ip_block_status status;
    357	const struct amdgpu_ip_block_version *version;
    358};
    359
    360int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
    361				       enum amd_ip_block_type type,
    362				       u32 major, u32 minor);
    363
    364struct amdgpu_ip_block *
    365amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
    366			      enum amd_ip_block_type type);
    367
    368int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
    369			       const struct amdgpu_ip_block_version *ip_block_version);
    370
    371/*
    372 * BIOS.
    373 */
    374bool amdgpu_get_bios(struct amdgpu_device *adev);
    375bool amdgpu_read_bios(struct amdgpu_device *adev);
    376bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
    377				     u8 *bios, u32 length_bytes);
    378/*
    379 * Clocks
    380 */
    381
    382#define AMDGPU_MAX_PPLL 3
    383
    384struct amdgpu_clock {
    385	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
    386	struct amdgpu_pll spll;
    387	struct amdgpu_pll mpll;
    388	/* 10 Khz units */
    389	uint32_t default_mclk;
    390	uint32_t default_sclk;
    391	uint32_t default_dispclk;
    392	uint32_t current_dispclk;
    393	uint32_t dp_extclk;
    394	uint32_t max_pixel_clock;
    395};
    396
    397/* sub-allocation manager, it has to be protected by another lock.
    398 * By conception this is an helper for other part of the driver
    399 * like the indirect buffer or semaphore, which both have their
    400 * locking.
    401 *
    402 * Principe is simple, we keep a list of sub allocation in offset
    403 * order (first entry has offset == 0, last entry has the highest
    404 * offset).
    405 *
    406 * When allocating new object we first check if there is room at
    407 * the end total_size - (last_object_offset + last_object_size) >=
    408 * alloc_size. If so we allocate new object there.
    409 *
    410 * When there is not enough room at the end, we start waiting for
    411 * each sub object until we reach object_offset+object_size >=
    412 * alloc_size, this object then become the sub object we return.
    413 *
    414 * Alignment can't be bigger than page size.
    415 *
    416 * Hole are not considered for allocation to keep things simple.
    417 * Assumption is that there won't be hole (all object on same
    418 * alignment).
    419 */
    420
    421#define AMDGPU_SA_NUM_FENCE_LISTS	32
    422
    423struct amdgpu_sa_manager {
    424	wait_queue_head_t	wq;
    425	struct amdgpu_bo	*bo;
    426	struct list_head	*hole;
    427	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];
    428	struct list_head	olist;
    429	unsigned		size;
    430	uint64_t		gpu_addr;
    431	void			*cpu_ptr;
    432	uint32_t		domain;
    433	uint32_t		align;
    434};
    435
    436/* sub-allocation buffer */
    437struct amdgpu_sa_bo {
    438	struct list_head		olist;
    439	struct list_head		flist;
    440	struct amdgpu_sa_manager	*manager;
    441	unsigned			soffset;
    442	unsigned			eoffset;
    443	struct dma_fence	        *fence;
    444};
    445
    446int amdgpu_fence_slab_init(void);
    447void amdgpu_fence_slab_fini(void);
    448
    449/*
    450 * IRQS.
    451 */
    452
    453struct amdgpu_flip_work {
    454	struct delayed_work		flip_work;
    455	struct work_struct		unpin_work;
    456	struct amdgpu_device		*adev;
    457	int				crtc_id;
    458	u32				target_vblank;
    459	uint64_t			base;
    460	struct drm_pending_vblank_event *event;
    461	struct amdgpu_bo		*old_abo;
    462	unsigned			shared_count;
    463	struct dma_fence		**shared;
    464	struct dma_fence_cb		cb;
    465	bool				async;
    466};
    467
    468
    469/*
    470 * file private structure
    471 */
    472
    473struct amdgpu_fpriv {
    474	struct amdgpu_vm	vm;
    475	struct amdgpu_bo_va	*prt_va;
    476	struct amdgpu_bo_va	*csa_va;
    477	struct mutex		bo_list_lock;
    478	struct idr		bo_list_handles;
    479	struct amdgpu_ctx_mgr	ctx_mgr;
    480};
    481
    482int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
    483
    484/*
    485 * Writeback
    486 */
    487#define AMDGPU_MAX_WB 256	/* Reserve at most 256 WB slots for amdgpu-owned rings. */
    488
    489struct amdgpu_wb {
    490	struct amdgpu_bo	*wb_obj;
    491	volatile uint32_t	*wb;
    492	uint64_t		gpu_addr;
    493	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
    494	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
    495};
    496
    497int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
    498void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
    499
    500/*
    501 * Benchmarking
    502 */
    503int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
    504
    505/*
    506 * ASIC specific register table accessible by UMD
    507 */
    508struct amdgpu_allowed_register_entry {
    509	uint32_t reg_offset;
    510	bool grbm_indexed;
    511};
    512
    513enum amd_reset_method {
    514	AMD_RESET_METHOD_NONE = -1,
    515	AMD_RESET_METHOD_LEGACY = 0,
    516	AMD_RESET_METHOD_MODE0,
    517	AMD_RESET_METHOD_MODE1,
    518	AMD_RESET_METHOD_MODE2,
    519	AMD_RESET_METHOD_BACO,
    520	AMD_RESET_METHOD_PCI,
    521};
    522
    523struct amdgpu_video_codec_info {
    524	u32 codec_type;
    525	u32 max_width;
    526	u32 max_height;
    527	u32 max_pixels_per_frame;
    528	u32 max_level;
    529};
    530
    531#define codec_info_build(type, width, height, level) \
    532			 .codec_type = type,\
    533			 .max_width = width,\
    534			 .max_height = height,\
    535			 .max_pixels_per_frame = height * width,\
    536			 .max_level = level,
    537
    538struct amdgpu_video_codecs {
    539	const u32 codec_count;
    540	const struct amdgpu_video_codec_info *codec_array;
    541};
    542
    543/*
    544 * ASIC specific functions.
    545 */
    546struct amdgpu_asic_funcs {
    547	bool (*read_disabled_bios)(struct amdgpu_device *adev);
    548	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
    549				   u8 *bios, u32 length_bytes);
    550	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
    551			     u32 sh_num, u32 reg_offset, u32 *value);
    552	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
    553	int (*reset)(struct amdgpu_device *adev);
    554	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
    555	/* get the reference clock */
    556	u32 (*get_xclk)(struct amdgpu_device *adev);
    557	/* MM block clocks */
    558	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
    559	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
    560	/* static power management */
    561	int (*get_pcie_lanes)(struct amdgpu_device *adev);
    562	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
    563	/* get config memsize register */
    564	u32 (*get_config_memsize)(struct amdgpu_device *adev);
    565	/* flush hdp write queue */
    566	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
    567	/* invalidate hdp read cache */
    568	void (*invalidate_hdp)(struct amdgpu_device *adev,
    569			       struct amdgpu_ring *ring);
    570	/* check if the asic needs a full reset of if soft reset will work */
    571	bool (*need_full_reset)(struct amdgpu_device *adev);
    572	/* initialize doorbell layout for specific asic*/
    573	void (*init_doorbell_index)(struct amdgpu_device *adev);
    574	/* PCIe bandwidth usage */
    575	void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
    576			       uint64_t *count1);
    577	/* do we need to reset the asic at init time (e.g., kexec) */
    578	bool (*need_reset_on_init)(struct amdgpu_device *adev);
    579	/* PCIe replay counter */
    580	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
    581	/* device supports BACO */
    582	bool (*supports_baco)(struct amdgpu_device *adev);
    583	/* pre asic_init quirks */
    584	void (*pre_asic_init)(struct amdgpu_device *adev);
    585	/* enter/exit umd stable pstate */
    586	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
    587	/* query video codecs */
    588	int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
    589				  const struct amdgpu_video_codecs **codecs);
    590};
    591
    592/*
    593 * IOCTL.
    594 */
    595int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
    596				struct drm_file *filp);
    597
    598int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
    599int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
    600				    struct drm_file *filp);
    601int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
    602int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
    603				struct drm_file *filp);
    604
    605/* VRAM scratch page for HDP bug, default vram page */
    606struct amdgpu_vram_scratch {
    607	struct amdgpu_bo		*robj;
    608	volatile uint32_t		*ptr;
    609	u64				gpu_addr;
    610};
    611
    612/*
    613 * CGS
    614 */
    615struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
    616void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
    617
    618/*
    619 * Core structure, functions and helpers.
    620 */
    621typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
    622typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
    623
    624typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
    625typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
    626
    627typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
    628typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
    629
    630struct amdgpu_mmio_remap {
    631	u32 reg_offset;
    632	resource_size_t bus_addr;
    633};
    634
    635/* Define the HW IP blocks will be used in driver , add more if necessary */
    636enum amd_hw_ip_block_type {
    637	GC_HWIP = 1,
    638	HDP_HWIP,
    639	SDMA0_HWIP,
    640	SDMA1_HWIP,
    641	SDMA2_HWIP,
    642	SDMA3_HWIP,
    643	SDMA4_HWIP,
    644	SDMA5_HWIP,
    645	SDMA6_HWIP,
    646	SDMA7_HWIP,
    647	LSDMA_HWIP,
    648	MMHUB_HWIP,
    649	ATHUB_HWIP,
    650	NBIO_HWIP,
    651	MP0_HWIP,
    652	MP1_HWIP,
    653	UVD_HWIP,
    654	VCN_HWIP = UVD_HWIP,
    655	JPEG_HWIP = VCN_HWIP,
    656	VCN1_HWIP,
    657	VCE_HWIP,
    658	DF_HWIP,
    659	DCE_HWIP,
    660	OSSSYS_HWIP,
    661	SMUIO_HWIP,
    662	PWR_HWIP,
    663	NBIF_HWIP,
    664	THM_HWIP,
    665	CLK_HWIP,
    666	UMC_HWIP,
    667	RSMU_HWIP,
    668	XGMI_HWIP,
    669	DCI_HWIP,
    670	MAX_HWIP
    671};
    672
    673#define HWIP_MAX_INSTANCE	11
    674
    675#define HW_ID_MAX		300
    676#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
    677#define IP_VERSION_MAJ(ver) ((ver) >> 16)
    678#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
    679#define IP_VERSION_REV(ver) ((ver) & 0xFF)
    680
    681struct amd_powerplay {
    682	void *pp_handle;
    683	const struct amd_pm_funcs *pp_funcs;
    684};
    685
    686struct ip_discovery_top;
    687
    688/* polaris10 kickers */
    689#define ASICID_IS_P20(did, rid)		(((did == 0x67DF) && \
    690					 ((rid == 0xE3) || \
    691					  (rid == 0xE4) || \
    692					  (rid == 0xE5) || \
    693					  (rid == 0xE7) || \
    694					  (rid == 0xEF))) || \
    695					 ((did == 0x6FDF) && \
    696					 ((rid == 0xE7) || \
    697					  (rid == 0xEF) || \
    698					  (rid == 0xFF))))
    699
    700#define ASICID_IS_P30(did, rid)		((did == 0x67DF) && \
    701					((rid == 0xE1) || \
    702					 (rid == 0xF7)))
    703
    704/* polaris11 kickers */
    705#define ASICID_IS_P21(did, rid)		(((did == 0x67EF) && \
    706					 ((rid == 0xE0) || \
    707					  (rid == 0xE5))) || \
    708					 ((did == 0x67FF) && \
    709					 ((rid == 0xCF) || \
    710					  (rid == 0xEF) || \
    711					  (rid == 0xFF))))
    712
    713#define ASICID_IS_P31(did, rid)		((did == 0x67EF) && \
    714					((rid == 0xE2)))
    715
    716/* polaris12 kickers */
    717#define ASICID_IS_P23(did, rid)		(((did == 0x6987) && \
    718					 ((rid == 0xC0) || \
    719					  (rid == 0xC1) || \
    720					  (rid == 0xC3) || \
    721					  (rid == 0xC7))) || \
    722					 ((did == 0x6981) && \
    723					 ((rid == 0x00) || \
    724					  (rid == 0x01) || \
    725					  (rid == 0x10))))
    726
    727struct amdgpu_mqd_prop {
    728	uint64_t mqd_gpu_addr;
    729	uint64_t hqd_base_gpu_addr;
    730	uint64_t rptr_gpu_addr;
    731	uint64_t wptr_gpu_addr;
    732	uint32_t queue_size;
    733	bool use_doorbell;
    734	uint32_t doorbell_index;
    735	uint64_t eop_gpu_addr;
    736	uint32_t hqd_pipe_priority;
    737	uint32_t hqd_queue_priority;
    738	bool hqd_active;
    739};
    740
    741struct amdgpu_mqd {
    742	unsigned mqd_size;
    743	int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
    744			struct amdgpu_mqd_prop *p);
    745};
    746
    747#define AMDGPU_RESET_MAGIC_NUM 64
    748#define AMDGPU_MAX_DF_PERFMONS 4
    749#define AMDGPU_PRODUCT_NAME_LEN 64
    750struct amdgpu_reset_domain;
    751
    752struct amdgpu_device {
    753	struct device			*dev;
    754	struct pci_dev			*pdev;
    755	struct drm_device		ddev;
    756
    757#ifdef CONFIG_DRM_AMD_ACP
    758	struct amdgpu_acp		acp;
    759#endif
    760	struct amdgpu_hive_info *hive;
    761	/* ASIC */
    762	enum amd_asic_type		asic_type;
    763	uint32_t			family;
    764	uint32_t			rev_id;
    765	uint32_t			external_rev_id;
    766	unsigned long			flags;
    767	unsigned long			apu_flags;
    768	int				usec_timeout;
    769	const struct amdgpu_asic_funcs	*asic_funcs;
    770	bool				shutdown;
    771	bool				need_swiotlb;
    772	bool				accel_working;
    773	struct notifier_block		acpi_nb;
    774	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
    775	struct debugfs_blob_wrapper     debugfs_vbios_blob;
    776	struct debugfs_blob_wrapper     debugfs_discovery_blob;
    777	struct mutex			srbm_mutex;
    778	/* GRBM index mutex. Protects concurrent access to GRBM index */
    779	struct mutex                    grbm_idx_mutex;
    780	struct dev_pm_domain		vga_pm_domain;
    781	bool				have_disp_power_ref;
    782	bool                            have_atomics_support;
    783
    784	/* BIOS */
    785	bool				is_atom_fw;
    786	uint8_t				*bios;
    787	uint32_t			bios_size;
    788	uint32_t			bios_scratch_reg_offset;
    789	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
    790
    791	/* Register/doorbell mmio */
    792	resource_size_t			rmmio_base;
    793	resource_size_t			rmmio_size;
    794	void __iomem			*rmmio;
    795	/* protects concurrent MM_INDEX/DATA based register access */
    796	spinlock_t mmio_idx_lock;
    797	struct amdgpu_mmio_remap        rmmio_remap;
    798	/* protects concurrent SMC based register access */
    799	spinlock_t smc_idx_lock;
    800	amdgpu_rreg_t			smc_rreg;
    801	amdgpu_wreg_t			smc_wreg;
    802	/* protects concurrent PCIE register access */
    803	spinlock_t pcie_idx_lock;
    804	amdgpu_rreg_t			pcie_rreg;
    805	amdgpu_wreg_t			pcie_wreg;
    806	amdgpu_rreg_t			pciep_rreg;
    807	amdgpu_wreg_t			pciep_wreg;
    808	amdgpu_rreg64_t			pcie_rreg64;
    809	amdgpu_wreg64_t			pcie_wreg64;
    810	/* protects concurrent UVD register access */
    811	spinlock_t uvd_ctx_idx_lock;
    812	amdgpu_rreg_t			uvd_ctx_rreg;
    813	amdgpu_wreg_t			uvd_ctx_wreg;
    814	/* protects concurrent DIDT register access */
    815	spinlock_t didt_idx_lock;
    816	amdgpu_rreg_t			didt_rreg;
    817	amdgpu_wreg_t			didt_wreg;
    818	/* protects concurrent gc_cac register access */
    819	spinlock_t gc_cac_idx_lock;
    820	amdgpu_rreg_t			gc_cac_rreg;
    821	amdgpu_wreg_t			gc_cac_wreg;
    822	/* protects concurrent se_cac register access */
    823	spinlock_t se_cac_idx_lock;
    824	amdgpu_rreg_t			se_cac_rreg;
    825	amdgpu_wreg_t			se_cac_wreg;
    826	/* protects concurrent ENDPOINT (audio) register access */
    827	spinlock_t audio_endpt_idx_lock;
    828	amdgpu_block_rreg_t		audio_endpt_rreg;
    829	amdgpu_block_wreg_t		audio_endpt_wreg;
    830	struct amdgpu_doorbell		doorbell;
    831
    832	/* clock/pll info */
    833	struct amdgpu_clock            clock;
    834
    835	/* MC */
    836	struct amdgpu_gmc		gmc;
    837	struct amdgpu_gart		gart;
    838	dma_addr_t			dummy_page_addr;
    839	struct amdgpu_vm_manager	vm_manager;
    840	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
    841	unsigned			num_vmhubs;
    842
    843	/* memory management */
    844	struct amdgpu_mman		mman;
    845	struct amdgpu_vram_scratch	vram_scratch;
    846	struct amdgpu_wb		wb;
    847	atomic64_t			num_bytes_moved;
    848	atomic64_t			num_evictions;
    849	atomic64_t			num_vram_cpu_page_faults;
    850	atomic_t			gpu_reset_counter;
    851	atomic_t			vram_lost_counter;
    852
    853	/* data for buffer migration throttling */
    854	struct {
    855		spinlock_t		lock;
    856		s64			last_update_us;
    857		s64			accum_us; /* accumulated microseconds */
    858		s64			accum_us_vis; /* for visible VRAM */
    859		u32			log2_max_MBps;
    860	} mm_stats;
    861
    862	/* display */
    863	bool				enable_virtual_display;
    864	struct amdgpu_vkms_output       *amdgpu_vkms_output;
    865	struct amdgpu_mode_info		mode_info;
    866	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
    867	struct work_struct		hotplug_work;
    868	struct amdgpu_irq_src		crtc_irq;
    869	struct amdgpu_irq_src		vline0_irq;
    870	struct amdgpu_irq_src		vupdate_irq;
    871	struct amdgpu_irq_src		pageflip_irq;
    872	struct amdgpu_irq_src		hpd_irq;
    873	struct amdgpu_irq_src		dmub_trace_irq;
    874	struct amdgpu_irq_src		dmub_outbox_irq;
    875
    876	/* rings */
    877	u64				fence_context;
    878	unsigned			num_rings;
    879	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
    880	bool				ib_pool_ready;
    881	struct amdgpu_sa_manager	ib_pools[AMDGPU_IB_POOL_MAX];
    882	struct amdgpu_sched		gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
    883
    884	/* interrupts */
    885	struct amdgpu_irq		irq;
    886
    887	/* powerplay */
    888	struct amd_powerplay		powerplay;
    889	struct amdgpu_pm		pm;
    890	u64				cg_flags;
    891	u32				pg_flags;
    892
    893	/* nbio */
    894	struct amdgpu_nbio		nbio;
    895
    896	/* hdp */
    897	struct amdgpu_hdp		hdp;
    898
    899	/* smuio */
    900	struct amdgpu_smuio		smuio;
    901
    902	/* mmhub */
    903	struct amdgpu_mmhub		mmhub;
    904
    905	/* gfxhub */
    906	struct amdgpu_gfxhub		gfxhub;
    907
    908	/* gfx */
    909	struct amdgpu_gfx		gfx;
    910
    911	/* sdma */
    912	struct amdgpu_sdma		sdma;
    913
    914	/* lsdma */
    915	struct amdgpu_lsdma		lsdma;
    916
    917	/* uvd */
    918	struct amdgpu_uvd		uvd;
    919
    920	/* vce */
    921	struct amdgpu_vce		vce;
    922
    923	/* vcn */
    924	struct amdgpu_vcn		vcn;
    925
    926	/* jpeg */
    927	struct amdgpu_jpeg		jpeg;
    928
    929	/* firmwares */
    930	struct amdgpu_firmware		firmware;
    931
    932	/* PSP */
    933	struct psp_context		psp;
    934
    935	/* GDS */
    936	struct amdgpu_gds		gds;
    937
    938	/* KFD */
    939	struct amdgpu_kfd_dev		kfd;
    940
    941	/* UMC */
    942	struct amdgpu_umc		umc;
    943
    944	/* display related functionality */
    945	struct amdgpu_display_manager dm;
    946
    947	/* mes */
    948	bool                            enable_mes;
    949	bool                            enable_mes_kiq;
    950	struct amdgpu_mes               mes;
    951	struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];
    952
    953	/* df */
    954	struct amdgpu_df                df;
    955
    956	/* MCA */
    957	struct amdgpu_mca               mca;
    958
    959	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
    960	uint32_t		        harvest_ip_mask;
    961	int				num_ip_blocks;
    962	struct mutex	mn_lock;
    963	DECLARE_HASHTABLE(mn_hash, 7);
    964
    965	/* tracking pinned memory */
    966	atomic64_t vram_pin_size;
    967	atomic64_t visible_pin_size;
    968	atomic64_t gart_pin_size;
    969
    970	/* soc15 register offset based on ip, instance and  segment */
    971	uint32_t		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
    972
    973	/* delayed work_func for deferring clockgating during resume */
    974	struct delayed_work     delayed_init_work;
    975
    976	struct amdgpu_virt	virt;
    977
    978	/* link all shadow bo */
    979	struct list_head                shadow_list;
    980	struct mutex                    shadow_list_lock;
    981
    982	/* record hw reset is performed */
    983	bool has_hw_reset;
    984	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];
    985
    986	/* s3/s4 mask */
    987	bool                            in_suspend;
    988	bool				in_s3;
    989	bool				in_s4;
    990	bool				in_s0ix;
    991
    992	enum pp_mp1_state               mp1_state;
    993	struct amdgpu_doorbell_index doorbell_index;
    994
    995	struct mutex			notifier_lock;
    996
    997	int asic_reset_res;
    998	struct work_struct		xgmi_reset_work;
    999	struct list_head		reset_list;
   1000
   1001	long				gfx_timeout;
   1002	long				sdma_timeout;
   1003	long				video_timeout;
   1004	long				compute_timeout;
   1005
   1006	uint64_t			unique_id;
   1007	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
   1008
   1009	/* enable runtime pm on the device */
   1010	bool                            runpm;
   1011	bool                            in_runpm;
   1012	bool                            has_pr3;
   1013
   1014	bool                            pm_sysfs_en;
   1015	bool                            ucode_sysfs_en;
   1016	bool                            psp_sysfs_en;
   1017
   1018	/* Chip product information */
   1019	char				product_number[16];
   1020	char				product_name[AMDGPU_PRODUCT_NAME_LEN];
   1021	char				serial[20];
   1022
   1023	atomic_t			throttling_logging_enabled;
   1024	struct ratelimit_state		throttling_logging_rs;
   1025	uint32_t                        ras_hw_enabled;
   1026	uint32_t                        ras_enabled;
   1027
   1028	bool                            no_hw_access;
   1029	struct pci_saved_state          *pci_state;
   1030	pci_channel_state_t		pci_channel_state;
   1031
   1032	struct amdgpu_reset_control     *reset_cntl;
   1033	uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
   1034
   1035	bool				ram_is_direct_mapped;
   1036
   1037	struct list_head                ras_list;
   1038
   1039	struct ip_discovery_top         *ip_top;
   1040
   1041	struct amdgpu_reset_domain	*reset_domain;
   1042
   1043	struct mutex			benchmark_mutex;
   1044
   1045	/* reset dump register */
   1046	uint32_t                        *reset_dump_reg_list;
   1047	int                             num_regs;
   1048
   1049	bool                            scpm_enabled;
   1050	uint32_t                        scpm_status;
   1051};
   1052
   1053static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
   1054{
   1055	return container_of(ddev, struct amdgpu_device, ddev);
   1056}
   1057
   1058static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
   1059{
   1060	return &adev->ddev;
   1061}
   1062
   1063static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
   1064{
   1065	return container_of(bdev, struct amdgpu_device, mman.bdev);
   1066}
   1067
   1068int amdgpu_device_init(struct amdgpu_device *adev,
   1069		       uint32_t flags);
   1070void amdgpu_device_fini_hw(struct amdgpu_device *adev);
   1071void amdgpu_device_fini_sw(struct amdgpu_device *adev);
   1072
   1073int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
   1074
   1075void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
   1076			     void *buf, size_t size, bool write);
   1077size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
   1078				 void *buf, size_t size, bool write);
   1079
   1080void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
   1081			       void *buf, size_t size, bool write);
   1082uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
   1083			    uint32_t reg, uint32_t acc_flags);
   1084void amdgpu_device_wreg(struct amdgpu_device *adev,
   1085			uint32_t reg, uint32_t v,
   1086			uint32_t acc_flags);
   1087void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
   1088			     uint32_t reg, uint32_t v);
   1089void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
   1090uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
   1091
   1092u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
   1093				u32 pcie_index, u32 pcie_data,
   1094				u32 reg_addr);
   1095u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
   1096				  u32 pcie_index, u32 pcie_data,
   1097				  u32 reg_addr);
   1098void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
   1099				 u32 pcie_index, u32 pcie_data,
   1100				 u32 reg_addr, u32 reg_data);
   1101void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
   1102				   u32 pcie_index, u32 pcie_data,
   1103				   u32 reg_addr, u64 reg_data);
   1104
   1105bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
   1106bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
   1107
   1108int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
   1109				 struct amdgpu_reset_context *reset_context);
   1110
   1111int amdgpu_do_asic_reset(struct list_head *device_list_handle,
   1112			 struct amdgpu_reset_context *reset_context);
   1113
   1114int emu_soc_asic_init(struct amdgpu_device *adev);
   1115
   1116/*
   1117 * Registers read & write functions.
   1118 */
   1119#define AMDGPU_REGS_NO_KIQ    (1<<1)
   1120#define AMDGPU_REGS_RLC	(1<<2)
   1121
   1122#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
   1123#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
   1124
   1125#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
   1126#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
   1127
   1128#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
   1129#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
   1130
   1131#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
   1132#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
   1133#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
   1134#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
   1135#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
   1136#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
   1137#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
   1138#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
   1139#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
   1140#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
   1141#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
   1142#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
   1143#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
   1144#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
   1145#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
   1146#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
   1147#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
   1148#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
   1149#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
   1150#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
   1151#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
   1152#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
   1153#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
   1154#define WREG32_P(reg, val, mask)				\
   1155	do {							\
   1156		uint32_t tmp_ = RREG32(reg);			\
   1157		tmp_ &= (mask);					\
   1158		tmp_ |= ((val) & ~(mask));			\
   1159		WREG32(reg, tmp_);				\
   1160	} while (0)
   1161#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
   1162#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
   1163#define WREG32_PLL_P(reg, val, mask)				\
   1164	do {							\
   1165		uint32_t tmp_ = RREG32_PLL(reg);		\
   1166		tmp_ &= (mask);					\
   1167		tmp_ |= ((val) & ~(mask));			\
   1168		WREG32_PLL(reg, tmp_);				\
   1169	} while (0)
   1170
   1171#define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
   1172	do {                                                    \
   1173		u32 tmp = RREG32_SMC(_Reg);                     \
   1174		tmp &= (_Mask);                                 \
   1175		tmp |= ((_Val) & ~(_Mask));                     \
   1176		WREG32_SMC(_Reg, tmp);                          \
   1177	} while (0)
   1178
   1179#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
   1180
   1181#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
   1182#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
   1183
   1184#define REG_SET_FIELD(orig_val, reg, field, field_val)			\
   1185	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
   1186	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
   1187
   1188#define REG_GET_FIELD(value, reg, field)				\
   1189	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
   1190
   1191#define WREG32_FIELD(reg, field, val)	\
   1192	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
   1193
   1194#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
   1195	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
   1196
   1197/*
   1198 * BIOS helpers.
   1199 */
   1200#define RBIOS8(i) (adev->bios[i])
   1201#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
   1202#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
   1203
   1204/*
   1205 * ASICs macro.
   1206 */
   1207#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
   1208#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
   1209#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
   1210#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
   1211#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
   1212#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
   1213#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
   1214#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
   1215#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
   1216#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
   1217#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
   1218#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
   1219#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
   1220#define amdgpu_asic_flush_hdp(adev, r) \
   1221	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
   1222#define amdgpu_asic_invalidate_hdp(adev, r) \
   1223	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
   1224	 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
   1225#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
   1226#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
   1227#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
   1228#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
   1229#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
   1230#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
   1231#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
   1232#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
   1233	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
   1234#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
   1235
   1236#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
   1237
   1238#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
   1239
   1240/* Common functions */
   1241bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
   1242bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
   1243int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
   1244			      struct amdgpu_job* job);
   1245int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
   1246			      struct amdgpu_job *job);
   1247void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
   1248int amdgpu_device_pci_reset(struct amdgpu_device *adev);
   1249bool amdgpu_device_need_post(struct amdgpu_device *adev);
   1250bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
   1251
   1252void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
   1253				  u64 num_vis_bytes);
   1254int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
   1255void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
   1256					     const u32 *registers,
   1257					     const u32 array_size);
   1258
   1259int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
   1260bool amdgpu_device_supports_atpx(struct drm_device *dev);
   1261bool amdgpu_device_supports_px(struct drm_device *dev);
   1262bool amdgpu_device_supports_boco(struct drm_device *dev);
   1263bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
   1264bool amdgpu_device_supports_baco(struct drm_device *dev);
   1265bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
   1266				      struct amdgpu_device *peer_adev);
   1267int amdgpu_device_baco_enter(struct drm_device *dev);
   1268int amdgpu_device_baco_exit(struct drm_device *dev);
   1269
   1270void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
   1271		struct amdgpu_ring *ring);
   1272void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
   1273		struct amdgpu_ring *ring);
   1274
   1275void amdgpu_device_halt(struct amdgpu_device *adev);
   1276u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
   1277				u32 reg);
   1278void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
   1279				u32 reg, u32 v);
   1280
   1281/* atpx handler */
   1282#if defined(CONFIG_VGA_SWITCHEROO)
   1283void amdgpu_register_atpx_handler(void);
   1284void amdgpu_unregister_atpx_handler(void);
   1285bool amdgpu_has_atpx_dgpu_power_cntl(void);
   1286bool amdgpu_is_atpx_hybrid(void);
   1287bool amdgpu_atpx_dgpu_req_power_for_displays(void);
   1288bool amdgpu_has_atpx(void);
   1289#else
   1290static inline void amdgpu_register_atpx_handler(void) {}
   1291static inline void amdgpu_unregister_atpx_handler(void) {}
   1292static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
   1293static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
   1294static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
   1295static inline bool amdgpu_has_atpx(void) { return false; }
   1296#endif
   1297
   1298#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
   1299void *amdgpu_atpx_get_dhandle(void);
   1300#else
   1301static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
   1302#endif
   1303
   1304/*
   1305 * KMS
   1306 */
   1307extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
   1308extern const int amdgpu_max_kms_ioctl;
   1309
   1310int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
   1311void amdgpu_driver_unload_kms(struct drm_device *dev);
   1312void amdgpu_driver_lastclose_kms(struct drm_device *dev);
   1313int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
   1314void amdgpu_driver_postclose_kms(struct drm_device *dev,
   1315				 struct drm_file *file_priv);
   1316void amdgpu_driver_release_kms(struct drm_device *dev);
   1317
   1318int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
   1319int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
   1320int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
   1321u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
   1322int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
   1323void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
   1324int amdgpu_info_ioctl(struct drm_device *dev, void *data,
   1325		      struct drm_file *filp);
   1326
   1327/*
   1328 * functions used by amdgpu_encoder.c
   1329 */
   1330struct amdgpu_afmt_acr {
   1331	u32 clock;
   1332
   1333	int n_32khz;
   1334	int cts_32khz;
   1335
   1336	int n_44_1khz;
   1337	int cts_44_1khz;
   1338
   1339	int n_48khz;
   1340	int cts_48khz;
   1341
   1342};
   1343
   1344struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
   1345
   1346/* amdgpu_acpi.c */
   1347
   1348/* ATCS Device/Driver State */
   1349#define AMDGPU_ATCS_PSC_DEV_STATE_D0		0
   1350#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT	3
   1351#define AMDGPU_ATCS_PSC_DRV_STATE_OPR		0
   1352#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR	1
   1353
   1354#if defined(CONFIG_ACPI)
   1355int amdgpu_acpi_init(struct amdgpu_device *adev);
   1356void amdgpu_acpi_fini(struct amdgpu_device *adev);
   1357bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
   1358bool amdgpu_acpi_is_power_shift_control_supported(void);
   1359int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
   1360						u8 perf_req, bool advertise);
   1361int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
   1362				    u8 dev_state, bool drv_state);
   1363int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
   1364int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
   1365
   1366void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
   1367void amdgpu_acpi_detect(void);
   1368#else
   1369static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
   1370static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
   1371static inline void amdgpu_acpi_detect(void) { }
   1372static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
   1373static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
   1374						  u8 dev_state, bool drv_state) { return 0; }
   1375static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
   1376						 enum amdgpu_ss ss_state) { return 0; }
   1377#endif
   1378
   1379#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
   1380bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
   1381bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
   1382bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
   1383#else
   1384static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
   1385static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
   1386static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
   1387#endif
   1388
   1389#if defined(CONFIG_DRM_AMD_DC)
   1390int amdgpu_dm_display_resume(struct amdgpu_device *adev );
   1391#else
   1392static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
   1393#endif
   1394
   1395
   1396void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
   1397void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
   1398
   1399pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
   1400					   pci_channel_state_t state);
   1401pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
   1402pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
   1403void amdgpu_pci_resume(struct pci_dev *pdev);
   1404
   1405bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
   1406bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
   1407
   1408bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
   1409
   1410int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
   1411			       enum amd_clockgating_state state);
   1412int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
   1413			       enum amd_powergating_state state);
   1414
   1415static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
   1416{
   1417	return amdgpu_gpu_recovery != 0 &&
   1418		adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
   1419		adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
   1420		adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
   1421		adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
   1422}
   1423
   1424#include "amdgpu_object.h"
   1425
   1426static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
   1427{
   1428       return adev->gmc.tmz_enabled;
   1429}
   1430
   1431int amdgpu_in_reset(struct amdgpu_device *adev);
   1432
   1433#endif