cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_fw_attestation.c (4429B)

      1/*
      2 * Copyright 2020 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#include <linux/debugfs.h>
     25#include <linux/firmware.h>
     26#include <linux/dma-mapping.h>
     27
     28#include "amdgpu.h"
     29#include "amdgpu_fw_attestation.h"
     30#include "amdgpu_psp.h"
     31#include "amdgpu_ucode.h"
     32#include "soc15_common.h"
     33
     34#define FW_ATTESTATION_DB_COOKIE        0x143b6a37
     35#define FW_ATTESTATION_RECORD_VALID  	1
     36#define FW_ATTESTATION_MAX_SIZE		4096
     37
     38typedef struct FW_ATT_DB_HEADER
     39{
     40	uint32_t AttDbVersion;           /* version of the fwar feature */
     41	uint32_t AttDbCookie;            /* cookie as an extra check for corrupt data */
     42} FW_ATT_DB_HEADER;
     43
     44typedef struct FW_ATT_RECORD
     45{
     46	uint16_t AttFwIdV1;              /* Legacy FW Type field */
     47	uint16_t AttFwIdV2;              /* V2 FW ID field */
     48	uint32_t AttFWVersion;           /* FW Version */
     49	uint16_t AttFWActiveFunctionID;  /* The VF ID (only in VF Attestation Table) */
     50	uint8_t  AttSource;              /* FW source indicator */
     51	uint8_t  RecordValid;            /* Indicates whether the record is a valid entry */
     52	uint32_t AttFwTaId;              /* Ta ID (only in TA Attestation Table) */
     53} FW_ATT_RECORD;
     54
     55static ssize_t amdgpu_fw_attestation_debugfs_read(struct file *f,
     56						  char __user *buf,
     57						  size_t size,
     58						  loff_t *pos)
     59{
     60	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
     61	uint64_t records_addr = 0;
     62	uint64_t vram_pos = 0;
     63	FW_ATT_DB_HEADER fw_att_hdr = {0};
     64	FW_ATT_RECORD fw_att_record = {0};
     65
     66	if (size < sizeof(FW_ATT_RECORD)) {
     67		DRM_WARN("FW attestation input buffer not enough memory");
     68		return -EINVAL;
     69	}
     70
     71	if ((*pos + sizeof(FW_ATT_DB_HEADER)) >= FW_ATTESTATION_MAX_SIZE) {
     72		DRM_WARN("FW attestation out of bounds");
     73		return 0;
     74	}
     75
     76	if (psp_get_fw_attestation_records_addr(&adev->psp, &records_addr)) {
     77		DRM_WARN("Failed to get FW attestation record address");
     78		return -EINVAL;
     79	}
     80
     81	vram_pos =  records_addr - adev->gmc.vram_start;
     82
     83	if (*pos == 0) {
     84		amdgpu_device_vram_access(adev,
     85					  vram_pos,
     86					  (uint32_t*)&fw_att_hdr,
     87					  sizeof(FW_ATT_DB_HEADER),
     88					  false);
     89
     90		if (fw_att_hdr.AttDbCookie != FW_ATTESTATION_DB_COOKIE) {
     91			DRM_WARN("Invalid FW attestation cookie");
     92			return -EINVAL;
     93		}
     94
     95		DRM_INFO("FW attestation version = 0x%X", fw_att_hdr.AttDbVersion);
     96	}
     97
     98	amdgpu_device_vram_access(adev,
     99				  vram_pos + sizeof(FW_ATT_DB_HEADER) + *pos,
    100				  (uint32_t*)&fw_att_record,
    101				  sizeof(FW_ATT_RECORD),
    102				  false);
    103
    104	if (fw_att_record.RecordValid != FW_ATTESTATION_RECORD_VALID)
    105		return 0;
    106
    107	if (copy_to_user(buf, (void*)&fw_att_record, sizeof(FW_ATT_RECORD)))
    108		return -EINVAL;
    109
    110	*pos += sizeof(FW_ATT_RECORD);
    111
    112	return sizeof(FW_ATT_RECORD);
    113}
    114
    115static const struct file_operations amdgpu_fw_attestation_debugfs_ops = {
    116	.owner = THIS_MODULE,
    117	.read = amdgpu_fw_attestation_debugfs_read,
    118	.write = NULL,
    119	.llseek = default_llseek
    120};
    121
    122static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)
    123{
    124	if (adev->flags & AMD_IS_APU)
    125		return 0;
    126
    127	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
    128		return 1;
    129
    130	return 0;
    131}
    132
    133void amdgpu_fw_attestation_debugfs_init(struct amdgpu_device *adev)
    134{
    135	if (!amdgpu_is_fw_attestation_supported(adev))
    136		return;
    137
    138	debugfs_create_file("amdgpu_fw_attestation",
    139			    S_IRUSR,
    140			    adev_to_drm(adev)->primary->debugfs_root,
    141			    adev,
    142			    &amdgpu_fw_attestation_debugfs_ops);
    143}