cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

amdgpu_gart.h (2609B)

      1/*
      2 * Copyright 2017 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef __AMDGPU_GART_H__
     25#define __AMDGPU_GART_H__
     26
     27#include <linux/types.h>
     28
     29/*
     30 * GART structures, functions & helpers
     31 */
     32struct amdgpu_device;
     33struct amdgpu_bo;
     34
     35#define AMDGPU_GPU_PAGE_SIZE 4096
     36#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
     37#define AMDGPU_GPU_PAGE_SHIFT 12
     38#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
     39
     40#define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
     41
     42struct amdgpu_gart {
     43	struct amdgpu_bo		*bo;
     44	/* CPU kmapped address of gart table */
     45	void				*ptr;
     46	unsigned			num_gpu_pages;
     47	unsigned			num_cpu_pages;
     48	unsigned			table_size;
     49
     50	/* Asic default pte flags */
     51	uint64_t			gart_pte_flags;
     52};
     53
     54int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
     55void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
     56int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
     57void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
     58int amdgpu_gart_init(struct amdgpu_device *adev);
     59void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
     60void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
     61			int pages);
     62void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
     63		     int pages, dma_addr_t *dma_addr, uint64_t flags,
     64		     void *dst);
     65void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
     66		      int pages, dma_addr_t *dma_addr, uint64_t flags);
     67void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
     68#endif