cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_imu.h (1817B)

      1/*
      2 * Copyright 2021 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef __AMDGPU_IMU_H__
     25#define __AMDGPU_IMU_H__
     26
     27struct amdgpu_imu_funcs {
     28    int (*init_microcode)(struct amdgpu_device *adev);
     29    int (*load_microcode)(struct amdgpu_device *adev);
     30    void (*setup_imu)(struct amdgpu_device *adev);
     31    int (*start_imu)(struct amdgpu_device *adev);
     32    void (*program_rlc_ram)(struct amdgpu_device *adev);
     33};
     34
     35struct imu_rlc_ram_golden {
     36    u32 hwip;
     37    u32 instance;
     38    u32 segment;
     39    u32 reg;
     40    u32 data;
     41    u32 addr_mask;
     42};
     43
     44#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
     45    { ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
     46
     47struct amdgpu_imu {
     48    const struct amdgpu_imu_funcs *funcs;
     49};
     50
     51#endif