cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_irq.h (4257B)

      1/*
      2 * Copyright 2014 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef __AMDGPU_IRQ_H__
     25#define __AMDGPU_IRQ_H__
     26
     27#include <linux/irqdomain.h>
     28#include "soc15_ih_clientid.h"
     29#include "amdgpu_ih.h"
     30
     31#define AMDGPU_MAX_IRQ_SRC_ID		0x100
     32#define AMDGPU_MAX_IRQ_CLIENT_ID	0x100
     33
     34#define AMDGPU_IRQ_CLIENTID_LEGACY	0
     35#define AMDGPU_IRQ_CLIENTID_MAX		SOC15_IH_CLIENTID_MAX
     36
     37#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW	4
     38
     39struct amdgpu_device;
     40
     41enum amdgpu_interrupt_state {
     42	AMDGPU_IRQ_STATE_DISABLE,
     43	AMDGPU_IRQ_STATE_ENABLE,
     44};
     45
     46struct amdgpu_iv_entry {
     47	struct amdgpu_ih_ring *ih;
     48	unsigned client_id;
     49	unsigned src_id;
     50	unsigned ring_id;
     51	unsigned vmid;
     52	unsigned vmid_src;
     53	uint64_t timestamp;
     54	unsigned timestamp_src;
     55	unsigned pasid;
     56	unsigned pasid_src;
     57	unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
     58	const uint32_t *iv_entry;
     59};
     60
     61struct amdgpu_irq_src {
     62	unsigned				num_types;
     63	atomic_t				*enabled_types;
     64	const struct amdgpu_irq_src_funcs	*funcs;
     65};
     66
     67struct amdgpu_irq_client {
     68	struct amdgpu_irq_src **sources;
     69};
     70
     71/* provided by interrupt generating IP blocks */
     72struct amdgpu_irq_src_funcs {
     73	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
     74		   unsigned type, enum amdgpu_interrupt_state state);
     75
     76	int (*process)(struct amdgpu_device *adev,
     77		       struct amdgpu_irq_src *source,
     78		       struct amdgpu_iv_entry *entry);
     79};
     80
     81struct amdgpu_irq {
     82	bool				installed;
     83	unsigned int			irq;
     84	spinlock_t			lock;
     85	/* interrupt sources */
     86	struct amdgpu_irq_client	client[AMDGPU_IRQ_CLIENTID_MAX];
     87
     88	/* status, etc. */
     89	bool				msi_enabled; /* msi enabled */
     90
     91	/* interrupt rings */
     92	struct amdgpu_ih_ring		ih, ih1, ih2, ih_soft;
     93	const struct amdgpu_ih_funcs    *ih_funcs;
     94	struct work_struct		ih1_work, ih2_work, ih_soft_work;
     95	struct amdgpu_irq_src		self_irq;
     96
     97	/* gen irq stuff */
     98	struct irq_domain		*domain; /* GPU irq controller domain */
     99	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
    100	uint32_t                        srbm_soft_reset;
    101};
    102
    103void amdgpu_irq_disable_all(struct amdgpu_device *adev);
    104
    105int amdgpu_irq_init(struct amdgpu_device *adev);
    106void amdgpu_irq_fini_sw(struct amdgpu_device *adev);
    107void amdgpu_irq_fini_hw(struct amdgpu_device *adev);
    108int amdgpu_irq_add_id(struct amdgpu_device *adev,
    109		      unsigned client_id, unsigned src_id,
    110		      struct amdgpu_irq_src *source);
    111void amdgpu_irq_dispatch(struct amdgpu_device *adev,
    112			 struct amdgpu_ih_ring *ih);
    113void amdgpu_irq_delegate(struct amdgpu_device *adev,
    114			 struct amdgpu_iv_entry *entry,
    115			 unsigned int num_dw);
    116int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    117		      unsigned type);
    118int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    119		   unsigned type);
    120int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    121		   unsigned type);
    122bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    123			unsigned type);
    124void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
    125
    126int amdgpu_irq_add_domain(struct amdgpu_device *adev);
    127void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
    128unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
    129
    130#endif