cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_job.h (3254B)

      1/*
      2 * Copyright 2018 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23#ifndef __AMDGPU_JOB_H__
     24#define __AMDGPU_JOB_H__
     25
     26#include <drm/gpu_scheduler.h>
     27#include "amdgpu_sync.h"
     28#include "amdgpu_ring.h"
     29
     30/* bit set means command submit involves a preamble IB */
     31#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0)
     32/* bit set means preamble IB is first presented in belonging context */
     33#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1)
     34/* bit set means context switch occured */
     35#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2)
     36/* bit set means IB is preempted */
     37#define AMDGPU_IB_PREEMPTED                 (1 << 3)
     38
     39#define to_amdgpu_job(sched_job)		\
     40		container_of((sched_job), struct amdgpu_job, base)
     41
     42#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
     43
     44struct amdgpu_fence;
     45enum amdgpu_ib_pool_type;
     46
     47struct amdgpu_job {
     48	struct drm_sched_job    base;
     49	struct amdgpu_vm	*vm;
     50	struct amdgpu_sync	sync;
     51	struct amdgpu_sync	sched_sync;
     52	struct dma_fence	hw_fence;
     53	struct dma_fence	*external_hw_fence;
     54	uint32_t		preamble_status;
     55	uint32_t                preemption_status;
     56	bool                    vm_needs_flush;
     57	uint64_t		vm_pd_addr;
     58	unsigned		vmid;
     59	unsigned		pasid;
     60	uint32_t		gds_base, gds_size;
     61	uint32_t		gws_base, gws_size;
     62	uint32_t		oa_base, oa_size;
     63	uint32_t		vram_lost_counter;
     64
     65	/* user fence handling */
     66	uint64_t		uf_addr;
     67	uint64_t		uf_sequence;
     68
     69	/* job_run_counter >= 1 means a resubmit job */
     70	uint32_t		job_run_counter;
     71
     72	uint32_t		num_ibs;
     73	struct amdgpu_ib	ibs[];
     74};
     75
     76int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
     77		     struct amdgpu_job **job, struct amdgpu_vm *vm);
     78int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
     79		enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);
     80void amdgpu_job_free_resources(struct amdgpu_job *job);
     81void amdgpu_job_free(struct amdgpu_job *job);
     82int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
     83		      void *owner, struct dma_fence **f);
     84int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
     85			     struct dma_fence **fence);
     86
     87void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
     88
     89#endif