amdgpu_umc.h (3622B)
1/* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef __AMDGPU_UMC_H__ 22#define __AMDGPU_UMC_H__ 23#include "amdgpu_ras.h" 24 25/* 26 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr 27 * is the index of 4KB block 28 */ 29#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) 30/* 31 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 32 * is the index of 8KB block 33 */ 34#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 35/* channel index is the index of 256B block */ 36#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 37/* offset in 256B block */ 38#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 39 40#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 41#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 42#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 43 44struct amdgpu_umc_ras { 45 struct amdgpu_ras_block_object ras_block; 46 void (*err_cnt_init)(struct amdgpu_device *adev); 47 bool (*query_ras_poison_mode)(struct amdgpu_device *adev); 48 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, 49 void *ras_error_status); 50 void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, 51 void *ras_error_status); 52}; 53 54struct amdgpu_umc_funcs { 55 void (*init_registers)(struct amdgpu_device *adev); 56}; 57 58struct amdgpu_umc { 59 /* max error count in one ras query call */ 60 uint32_t max_ras_err_cnt_per_query; 61 /* number of umc channel instance with memory map register access */ 62 uint32_t channel_inst_num; 63 /* number of umc instance with memory map register access */ 64 uint32_t umc_inst_num; 65 /* UMC regiser per channel offset */ 66 uint32_t channel_offs; 67 /* channel index table of interleaved memory */ 68 const uint32_t *channel_idx_tbl; 69 struct ras_common_if *ras_if; 70 71 const struct amdgpu_umc_funcs *funcs; 72 struct amdgpu_umc_ras *ras; 73}; 74 75int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 76int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 77 void *ras_error_status, 78 bool reset); 79int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 80 struct amdgpu_irq_src *source, 81 struct amdgpu_iv_entry *entry); 82void amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 83 uint64_t err_addr, 84 uint64_t retired_page, 85 uint32_t channel_index, 86 uint32_t umc_inst); 87 88int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 89 void *ras_error_status, 90 struct amdgpu_iv_entry *entry); 91#endif