amdgpu_virt.h (12200B)
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24#ifndef AMDGPU_VIRT_H 25#define AMDGPU_VIRT_H 26 27#include "amdgv_sriovmsg.h" 28 29#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 35/* flags for indirect register access path supported by rlcg for sriov */ 36#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 37#define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 38#define AMDGPU_RLCG_GC_READ (0x1 << 28) 39#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 40 41/* error code for indirect register access path supported by rlcg for sriov */ 42#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 43#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 44#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 45 46#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 47 48/* all asic after AI use this offset */ 49#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 50/* tonga/fiji use this offset */ 51#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 52 53enum amdgpu_sriov_vf_mode { 54 SRIOV_VF_MODE_BARE_METAL = 0, 55 SRIOV_VF_MODE_ONE_VF, 56 SRIOV_VF_MODE_MULTI_VF, 57}; 58 59struct amdgpu_mm_table { 60 struct amdgpu_bo *bo; 61 uint32_t *cpu_addr; 62 uint64_t gpu_addr; 63}; 64 65#define AMDGPU_VF_ERROR_ENTRY_SIZE 16 66 67/* struct error_entry - amdgpu VF error information. */ 68struct amdgpu_vf_error_buffer { 69 struct mutex lock; 70 int read_count; 71 int write_count; 72 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 73 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 74 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 75}; 76 77/** 78 * struct amdgpu_virt_ops - amdgpu device virt operations 79 */ 80struct amdgpu_virt_ops { 81 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 82 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 83 int (*req_init_data)(struct amdgpu_device *adev); 84 int (*reset_gpu)(struct amdgpu_device *adev); 85 int (*wait_reset)(struct amdgpu_device *adev); 86 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 87}; 88 89/* 90 * Firmware Reserve Frame buffer 91 */ 92struct amdgpu_virt_fw_reserve { 93 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 94 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 95 unsigned int checksum_key; 96}; 97 98/* 99 * Legacy GIM header 100 * 101 * Defination between PF and VF 102 * Structures forcibly aligned to 4 to keep the same style as PF. 103 */ 104#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 105 106#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 107 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 108 109enum AMDGIM_FEATURE_FLAG { 110 /* GIM supports feature of Error log collecting */ 111 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 112 /* GIM supports feature of loading uCodes */ 113 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 114 /* VRAM LOST by GIM */ 115 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 116 /* MM bandwidth */ 117 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 118 /* PP ONE VF MODE in GIM */ 119 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 120 /* Indirect Reg Access enabled */ 121 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 122}; 123 124enum AMDGIM_REG_ACCESS_FLAG { 125 /* Use PSP to program IH_RB_CNTL */ 126 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 127 /* Use RLC to program MMHUB regs */ 128 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 129 /* Use RLC to program GC regs */ 130 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 131}; 132 133struct amdgim_pf2vf_info_v1 { 134 /* header contains size and version */ 135 struct amd_sriov_msg_pf2vf_info_header header; 136 /* max_width * max_height */ 137 unsigned int uvd_enc_max_pixels_count; 138 /* 16x16 pixels/sec, codec independent */ 139 unsigned int uvd_enc_max_bandwidth; 140 /* max_width * max_height */ 141 unsigned int vce_enc_max_pixels_count; 142 /* 16x16 pixels/sec, codec independent */ 143 unsigned int vce_enc_max_bandwidth; 144 /* MEC FW position in kb from the start of visible frame buffer */ 145 unsigned int mecfw_kboffset; 146 /* The features flags of the GIM driver supports. */ 147 unsigned int feature_flags; 148 /* use private key from mailbox 2 to create chueksum */ 149 unsigned int checksum; 150} __aligned(4); 151 152struct amdgim_vf2pf_info_v1 { 153 /* header contains size and version */ 154 struct amd_sriov_msg_vf2pf_info_header header; 155 /* driver version */ 156 char driver_version[64]; 157 /* driver certification, 1=WHQL, 0=None */ 158 unsigned int driver_cert; 159 /* guest OS type and version: need a define */ 160 unsigned int os_info; 161 /* in the unit of 1M */ 162 unsigned int fb_usage; 163 /* guest gfx engine usage percentage */ 164 unsigned int gfx_usage; 165 /* guest gfx engine health percentage */ 166 unsigned int gfx_health; 167 /* guest compute engine usage percentage */ 168 unsigned int compute_usage; 169 /* guest compute engine health percentage */ 170 unsigned int compute_health; 171 /* guest vce engine usage percentage. 0xffff means N/A. */ 172 unsigned int vce_enc_usage; 173 /* guest vce engine health percentage. 0xffff means N/A. */ 174 unsigned int vce_enc_health; 175 /* guest uvd engine usage percentage. 0xffff means N/A. */ 176 unsigned int uvd_enc_usage; 177 /* guest uvd engine usage percentage. 0xffff means N/A. */ 178 unsigned int uvd_enc_health; 179 unsigned int checksum; 180} __aligned(4); 181 182struct amdgim_vf2pf_info_v2 { 183 /* header contains size and version */ 184 struct amd_sriov_msg_vf2pf_info_header header; 185 uint32_t checksum; 186 /* driver version */ 187 uint8_t driver_version[64]; 188 /* driver certification, 1=WHQL, 0=None */ 189 uint32_t driver_cert; 190 /* guest OS type and version: need a define */ 191 uint32_t os_info; 192 /* in the unit of 1M */ 193 uint32_t fb_usage; 194 /* guest gfx engine usage percentage */ 195 uint32_t gfx_usage; 196 /* guest gfx engine health percentage */ 197 uint32_t gfx_health; 198 /* guest compute engine usage percentage */ 199 uint32_t compute_usage; 200 /* guest compute engine health percentage */ 201 uint32_t compute_health; 202 /* guest vce engine usage percentage. 0xffff means N/A. */ 203 uint32_t vce_enc_usage; 204 /* guest vce engine health percentage. 0xffff means N/A. */ 205 uint32_t vce_enc_health; 206 /* guest uvd engine usage percentage. 0xffff means N/A. */ 207 uint32_t uvd_enc_usage; 208 /* guest uvd engine usage percentage. 0xffff means N/A. */ 209 uint32_t uvd_enc_health; 210 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 211} __aligned(4); 212 213struct amdgpu_virt_ras_err_handler_data { 214 /* point to bad page records array */ 215 struct eeprom_table_record *bps; 216 /* point to reserved bo array */ 217 struct amdgpu_bo **bps_bo; 218 /* the count of entries */ 219 int count; 220 /* last reserved entry's index + 1 */ 221 int last_reserved; 222}; 223 224/* GPU virtualization */ 225struct amdgpu_virt { 226 uint32_t caps; 227 struct amdgpu_bo *csa_obj; 228 void *csa_cpu_addr; 229 bool chained_ib_support; 230 uint32_t reg_val_offs; 231 struct amdgpu_irq_src ack_irq; 232 struct amdgpu_irq_src rcv_irq; 233 struct work_struct flr_work; 234 struct amdgpu_mm_table mm_table; 235 const struct amdgpu_virt_ops *ops; 236 struct amdgpu_vf_error_buffer vf_errors; 237 struct amdgpu_virt_fw_reserve fw_reserve; 238 uint32_t gim_feature; 239 uint32_t reg_access_mode; 240 int req_init_data_ver; 241 bool tdr_debug; 242 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 243 bool ras_init_done; 244 uint32_t reg_access; 245 246 /* vf2pf message */ 247 struct delayed_work vf2pf_work; 248 uint32_t vf2pf_update_interval_ms; 249 250 /* multimedia bandwidth config */ 251 bool is_mm_bw_enabled; 252 uint32_t decode_max_dimension_pixels; 253 uint32_t decode_max_frame_pixels; 254 uint32_t encode_max_dimension_pixels; 255 uint32_t encode_max_frame_pixels; 256}; 257 258struct amdgpu_video_codec_info; 259 260#define amdgpu_sriov_enabled(adev) \ 261((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 262 263#define amdgpu_sriov_vf(adev) \ 264((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 265 266#define amdgpu_sriov_bios(adev) \ 267((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 268 269#define amdgpu_sriov_runtime(adev) \ 270((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 271 272#define amdgpu_sriov_fullaccess(adev) \ 273(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 274 275#define amdgpu_sriov_reg_indirect_en(adev) \ 276(amdgpu_sriov_vf((adev)) && \ 277 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 278 279#define amdgpu_sriov_reg_indirect_ih(adev) \ 280(amdgpu_sriov_vf((adev)) && \ 281 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 282 283#define amdgpu_sriov_reg_indirect_mmhub(adev) \ 284(amdgpu_sriov_vf((adev)) && \ 285 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 286 287#define amdgpu_sriov_reg_indirect_gc(adev) \ 288(amdgpu_sriov_vf((adev)) && \ 289 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 290 291#define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 292 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 293 294#define amdgpu_passthrough(adev) \ 295((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 296 297static inline bool is_virtual_machine(void) 298{ 299#if defined(CONFIG_X86) 300 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 301#elif defined(CONFIG_ARM64) 302 return !is_kernel_in_hyp_mode(); 303#else 304 return false; 305#endif 306} 307 308#define amdgpu_sriov_is_pp_one_vf(adev) \ 309 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 310#define amdgpu_sriov_is_debug(adev) \ 311 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 312#define amdgpu_sriov_is_normal(adev) \ 313 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 314bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 315void amdgpu_virt_init_setting(struct amdgpu_device *adev); 316void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 317 uint32_t reg0, uint32_t rreg1, 318 uint32_t ref, uint32_t mask); 319int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 320int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 321int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 322void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 323int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 324int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 325void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 326void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 327void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 328void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 329void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 330void amdgpu_detect_virtualization(struct amdgpu_device *adev); 331 332bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 333int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 334void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 335 336enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 337 338void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 339 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 340 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 341void amdgpu_sriov_wreg(struct amdgpu_device *adev, 342 u32 offset, u32 value, 343 u32 acc_flags, u32 hwip); 344u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 345 u32 offset, u32 acc_flags, u32 hwip); 346#endif