cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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athub_v3_0.c (2993B)

      1/*
      2 * Copyright 2021 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#include "amdgpu.h"
     25#include "athub_v3_0.h"
     26#include "athub/athub_3_0_0_offset.h"
     27#include "athub/athub_3_0_0_sh_mask.h"
     28#include "navi10_enum.h"
     29#include "soc15_common.h"
     30
     31static void
     32athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
     33					    bool enable)
     34{
     35	uint32_t def, data;
     36
     37	def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
     38
     39	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
     40		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
     41	else
     42		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
     43
     44	if (def != data)
     45		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
     46}
     47
     48static void
     49athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
     50					   bool enable)
     51{
     52	uint32_t def, data;
     53
     54	def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
     55
     56	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
     57		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
     58	else
     59		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
     60
     61	if (def != data)
     62		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
     63}
     64
     65int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
     66			       enum amd_clockgating_state state)
     67{
     68	if (amdgpu_sriov_vf(adev))
     69		return 0;
     70
     71	switch (adev->ip_versions[ATHUB_HWIP][0]) {
     72	case IP_VERSION(3, 0, 0):
     73	case IP_VERSION(3, 0, 2):
     74		athub_v3_0_update_medium_grain_clock_gating(adev,
     75				state == AMD_CG_STATE_GATE);
     76		athub_v3_0_update_medium_grain_light_sleep(adev,
     77				state == AMD_CG_STATE_GATE);
     78		break;
     79	default:
     80		break;
     81	}
     82
     83	return 0;
     84}
     85
     86void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
     87{
     88	int data;
     89
     90	/* AMD_CG_SUPPORT_ATHUB_MGCG */
     91	data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
     92	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
     93		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
     94
     95	/* AMD_CG_SUPPORT_ATHUB_LS */
     96	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
     97		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
     98}