cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mxgpu_ai.h (2323B)


      1/*
      2 * Copyright 2014 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef __MXGPU_AI_H__
     25#define __MXGPU_AI_H__
     26
     27#define AI_MAILBOX_POLL_ACK_TIMEDOUT	500
     28#define AI_MAILBOX_POLL_MSG_TIMEDOUT	6000
     29#define AI_MAILBOX_POLL_FLR_TIMEDOUT	10000
     30#define AI_MAILBOX_POLL_MSG_REP_MAX	11
     31
     32enum idh_request {
     33	IDH_REQ_GPU_INIT_ACCESS = 1,
     34	IDH_REL_GPU_INIT_ACCESS,
     35	IDH_REQ_GPU_FINI_ACCESS,
     36	IDH_REL_GPU_FINI_ACCESS,
     37	IDH_REQ_GPU_RESET_ACCESS,
     38	IDH_REQ_GPU_INIT_DATA,
     39
     40	IDH_LOG_VF_ERROR       = 200,
     41	IDH_READY_TO_RESET 	= 201,
     42};
     43
     44enum idh_event {
     45	IDH_CLR_MSG_BUF	= 0,
     46	IDH_READY_TO_ACCESS_GPU,
     47	IDH_FLR_NOTIFICATION,
     48	IDH_FLR_NOTIFICATION_CMPL,
     49	IDH_SUCCESS,
     50	IDH_FAIL,
     51	IDH_QUERY_ALIVE,
     52	IDH_REQ_GPU_INIT_DATA_READY,
     53
     54	IDH_TEXT_MESSAGE = 255,
     55};
     56
     57extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;
     58
     59void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev);
     60int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev);
     61int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev);
     62void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev);
     63
     64#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
     65#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1
     66
     67#endif