cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sdma_v5_0.c (63623B)


      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#include <linux/delay.h>
     25#include <linux/firmware.h>
     26#include <linux/module.h>
     27#include <linux/pci.h>
     28
     29#include "amdgpu.h"
     30#include "amdgpu_ucode.h"
     31#include "amdgpu_trace.h"
     32
     33#include "gc/gc_10_1_0_offset.h"
     34#include "gc/gc_10_1_0_sh_mask.h"
     35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
     36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
     37
     38#include "soc15_common.h"
     39#include "soc15.h"
     40#include "navi10_sdma_pkt_open.h"
     41#include "nbio_v2_3.h"
     42#include "sdma_common.h"
     43#include "sdma_v5_0.h"
     44
     45MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
     46MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
     47
     48MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
     49MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
     50
     51MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
     52MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
     53
     54MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
     55MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
     56
     57#define SDMA1_REG_OFFSET 0x600
     58#define SDMA0_HYP_DEC_REG_START 0x5880
     59#define SDMA0_HYP_DEC_REG_END 0x5893
     60#define SDMA1_HYP_DEC_REG_OFFSET 0x20
     61
     62static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
     63static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
     64static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
     65static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
     66
     67static const struct soc15_reg_golden golden_settings_sdma_5[] = {
     68	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
     69	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     70	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     71	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     72	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     73	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     74	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     75	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     76	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     77	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     78	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     79	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
     80	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
     81	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     82	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     83	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     84	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     85	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     86	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     87	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     88	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     89	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     90	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     91	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
     92};
     93
     94static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
     95	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     96	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     97	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     98	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
     99	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    100	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    101	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    102	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    103	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    104	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    105	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    106	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    107	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    108	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    109	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    110	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    111	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    112	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    113	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    114	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    115};
    116
    117static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
    118	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
    119	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
    120};
    121
    122static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
    123	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    124	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    125};
    126
    127static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
    128	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    129	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
    130	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
    131	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
    132	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
    133	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    134};
    135
    136static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
    137	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
    138	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
    139	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
    140	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    141	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    142	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    143	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    144	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    145	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    146	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    147	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    148	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    149	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    150	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
    151	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
    152	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
    153	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
    154	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    155	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    156	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    157	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    158	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    159	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    160	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    161	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    162	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    163	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
    164	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
    165};
    166
    167static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
    168{
    169	u32 base;
    170
    171	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
    172	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
    173		base = adev->reg_offset[GC_HWIP][0][1];
    174		if (instance == 1)
    175			internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
    176	} else {
    177		base = adev->reg_offset[GC_HWIP][0][0];
    178		if (instance == 1)
    179			internal_offset += SDMA1_REG_OFFSET;
    180	}
    181
    182	return base + internal_offset;
    183}
    184
    185static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
    186{
    187	switch (adev->ip_versions[SDMA0_HWIP][0]) {
    188	case IP_VERSION(5, 0, 0):
    189		soc15_program_register_sequence(adev,
    190						golden_settings_sdma_5,
    191						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
    192		soc15_program_register_sequence(adev,
    193						golden_settings_sdma_nv10,
    194						(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
    195		break;
    196	case IP_VERSION(5, 0, 2):
    197		soc15_program_register_sequence(adev,
    198						golden_settings_sdma_5,
    199						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
    200		soc15_program_register_sequence(adev,
    201						golden_settings_sdma_nv14,
    202						(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
    203		break;
    204	case IP_VERSION(5, 0, 5):
    205		if (amdgpu_sriov_vf(adev))
    206			soc15_program_register_sequence(adev,
    207							golden_settings_sdma_5_sriov,
    208							(const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
    209		else
    210			soc15_program_register_sequence(adev,
    211							golden_settings_sdma_5,
    212							(const u32)ARRAY_SIZE(golden_settings_sdma_5));
    213		soc15_program_register_sequence(adev,
    214						golden_settings_sdma_nv12,
    215						(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
    216		break;
    217	case IP_VERSION(5, 0, 1):
    218		soc15_program_register_sequence(adev,
    219						golden_settings_sdma_cyan_skillfish,
    220						(const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
    221		break;
    222	default:
    223		break;
    224	}
    225}
    226
    227/**
    228 * sdma_v5_0_init_microcode - load ucode images from disk
    229 *
    230 * @adev: amdgpu_device pointer
    231 *
    232 * Use the firmware interface to load the ucode images into
    233 * the driver (not loaded into hw).
    234 * Returns 0 on success, error on failure.
    235 */
    236
    237// emulation only, won't work on real chip
    238// navi10 real chip need to use PSP to load firmware
    239static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
    240{
    241	const char *chip_name;
    242	char fw_name[40];
    243	int err = 0, i;
    244	struct amdgpu_firmware_info *info = NULL;
    245	const struct common_firmware_header *header = NULL;
    246	const struct sdma_firmware_header_v1_0 *hdr;
    247
    248	if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
    249		return 0;
    250
    251	DRM_DEBUG("\n");
    252
    253	switch (adev->ip_versions[SDMA0_HWIP][0]) {
    254	case IP_VERSION(5, 0, 0):
    255		chip_name = "navi10";
    256		break;
    257	case IP_VERSION(5, 0, 2):
    258		chip_name = "navi14";
    259		break;
    260	case IP_VERSION(5, 0, 5):
    261		chip_name = "navi12";
    262		break;
    263	case IP_VERSION(5, 0, 1):
    264		chip_name = "cyan_skillfish2";
    265		break;
    266	default:
    267		BUG();
    268	}
    269
    270	for (i = 0; i < adev->sdma.num_instances; i++) {
    271		if (i == 0)
    272			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
    273		else
    274			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
    275		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
    276		if (err)
    277			goto out;
    278		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
    279		if (err)
    280			goto out;
    281		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
    282		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
    283		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
    284		if (adev->sdma.instance[i].feature_version >= 20)
    285			adev->sdma.instance[i].burst_nop = true;
    286		DRM_DEBUG("psp_load == '%s'\n",
    287				adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
    288
    289		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
    290			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
    291			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
    292			info->fw = adev->sdma.instance[i].fw;
    293			header = (const struct common_firmware_header *)info->fw->data;
    294			adev->firmware.fw_size +=
    295				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
    296		}
    297	}
    298out:
    299	if (err) {
    300		DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
    301		for (i = 0; i < adev->sdma.num_instances; i++) {
    302			release_firmware(adev->sdma.instance[i].fw);
    303			adev->sdma.instance[i].fw = NULL;
    304		}
    305	}
    306	return err;
    307}
    308
    309static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
    310{
    311	unsigned ret;
    312
    313	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
    314	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
    315	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
    316	amdgpu_ring_write(ring, 1);
    317	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
    318	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
    319
    320	return ret;
    321}
    322
    323static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
    324					   unsigned offset)
    325{
    326	unsigned cur;
    327
    328	BUG_ON(offset > ring->buf_mask);
    329	BUG_ON(ring->ring[offset] != 0x55aa55aa);
    330
    331	cur = (ring->wptr - 1) & ring->buf_mask;
    332	if (cur > offset)
    333		ring->ring[offset] = cur - offset;
    334	else
    335		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
    336}
    337
    338/**
    339 * sdma_v5_0_ring_get_rptr - get the current read pointer
    340 *
    341 * @ring: amdgpu ring pointer
    342 *
    343 * Get the current rptr from the hardware (NAVI10+).
    344 */
    345static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
    346{
    347	u64 *rptr;
    348
    349	/* XXX check if swapping is necessary on BE */
    350	rptr = (u64 *)ring->rptr_cpu_addr;
    351
    352	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
    353	return ((*rptr) >> 2);
    354}
    355
    356/**
    357 * sdma_v5_0_ring_get_wptr - get the current write pointer
    358 *
    359 * @ring: amdgpu ring pointer
    360 *
    361 * Get the current wptr from the hardware (NAVI10+).
    362 */
    363static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
    364{
    365	struct amdgpu_device *adev = ring->adev;
    366	u64 wptr;
    367
    368	if (ring->use_doorbell) {
    369		/* XXX check if swapping is necessary on BE */
    370		wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
    371		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
    372	} else {
    373		wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
    374		wptr = wptr << 32;
    375		wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
    376		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
    377	}
    378
    379	return wptr >> 2;
    380}
    381
    382/**
    383 * sdma_v5_0_ring_set_wptr - commit the write pointer
    384 *
    385 * @ring: amdgpu ring pointer
    386 *
    387 * Write the wptr back to the hardware (NAVI10+).
    388 */
    389static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
    390{
    391	struct amdgpu_device *adev = ring->adev;
    392
    393	DRM_DEBUG("Setting write pointer\n");
    394	if (ring->use_doorbell) {
    395		DRM_DEBUG("Using doorbell -- "
    396				"wptr_offs == 0x%08x "
    397				"lower_32_bits(ring->wptr << 2) == 0x%08x "
    398				"upper_32_bits(ring->wptr << 2) == 0x%08x\n",
    399				ring->wptr_offs,
    400				lower_32_bits(ring->wptr << 2),
    401				upper_32_bits(ring->wptr << 2));
    402		/* XXX check if swapping is necessary on BE */
    403		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
    404			     ring->wptr << 2);
    405		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
    406				ring->doorbell_index, ring->wptr << 2);
    407		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
    408	} else {
    409		DRM_DEBUG("Not using doorbell -- "
    410				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
    411				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
    412				ring->me,
    413				lower_32_bits(ring->wptr << 2),
    414				ring->me,
    415				upper_32_bits(ring->wptr << 2));
    416		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
    417			lower_32_bits(ring->wptr << 2));
    418		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
    419			upper_32_bits(ring->wptr << 2));
    420	}
    421}
    422
    423static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
    424{
    425	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
    426	int i;
    427
    428	for (i = 0; i < count; i++)
    429		if (sdma && sdma->burst_nop && (i == 0))
    430			amdgpu_ring_write(ring, ring->funcs->nop |
    431				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
    432		else
    433			amdgpu_ring_write(ring, ring->funcs->nop);
    434}
    435
    436/**
    437 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
    438 *
    439 * @ring: amdgpu ring pointer
    440 * @job: job to retrieve vmid from
    441 * @ib: IB object to schedule
    442 * @flags: unused
    443 *
    444 * Schedule an IB in the DMA ring (NAVI10).
    445 */
    446static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
    447				   struct amdgpu_job *job,
    448				   struct amdgpu_ib *ib,
    449				   uint32_t flags)
    450{
    451	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
    452	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
    453
    454	/* An IB packet must end on a 8 DW boundary--the next dword
    455	 * must be on a 8-dword boundary. Our IB packet below is 6
    456	 * dwords long, thus add x number of NOPs, such that, in
    457	 * modular arithmetic,
    458	 * wptr + 6 + x = 8k, k >= 0, which in C is,
    459	 * (wptr + 6 + x) % 8 = 0.
    460	 * The expression below, is a solution of x.
    461	 */
    462	sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
    463
    464	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
    465			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
    466	/* base must be 32 byte aligned */
    467	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
    468	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
    469	amdgpu_ring_write(ring, ib->length_dw);
    470	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
    471	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
    472}
    473
    474/**
    475 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
    476 *
    477 * @ring: amdgpu ring pointer
    478 *
    479 * flush the IB by graphics cache rinse.
    480 */
    481static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
    482{
    483	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
    484			    SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
    485			    SDMA_GCR_GLI_INV(1);
    486
    487	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
    488	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
    489	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
    490	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
    491			  SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
    492	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
    493			  SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
    494	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
    495			  SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
    496}
    497
    498/**
    499 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
    500 *
    501 * @ring: amdgpu ring pointer
    502 *
    503 * Emit an hdp flush packet on the requested DMA ring.
    504 */
    505static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
    506{
    507	struct amdgpu_device *adev = ring->adev;
    508	u32 ref_and_mask = 0;
    509	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
    510
    511	if (ring->me == 0)
    512		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
    513	else
    514		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
    515
    516	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
    517			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
    518			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
    519	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
    520	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
    521	amdgpu_ring_write(ring, ref_and_mask); /* reference */
    522	amdgpu_ring_write(ring, ref_and_mask); /* mask */
    523	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
    524			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
    525}
    526
    527/**
    528 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
    529 *
    530 * @ring: amdgpu ring pointer
    531 * @addr: address
    532 * @seq: sequence number
    533 * @flags: fence related flags
    534 *
    535 * Add a DMA fence packet to the ring to write
    536 * the fence seq number and DMA trap packet to generate
    537 * an interrupt if needed (NAVI10).
    538 */
    539static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
    540				      unsigned flags)
    541{
    542	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
    543	/* write the fence */
    544	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
    545			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
    546	/* zero in first two bits */
    547	BUG_ON(addr & 0x3);
    548	amdgpu_ring_write(ring, lower_32_bits(addr));
    549	amdgpu_ring_write(ring, upper_32_bits(addr));
    550	amdgpu_ring_write(ring, lower_32_bits(seq));
    551
    552	/* optionally write high bits as well */
    553	if (write64bit) {
    554		addr += 4;
    555		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
    556				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
    557		/* zero in first two bits */
    558		BUG_ON(addr & 0x3);
    559		amdgpu_ring_write(ring, lower_32_bits(addr));
    560		amdgpu_ring_write(ring, upper_32_bits(addr));
    561		amdgpu_ring_write(ring, upper_32_bits(seq));
    562	}
    563
    564	if (flags & AMDGPU_FENCE_FLAG_INT) {
    565		uint32_t ctx = ring->is_mes_queue ?
    566			(ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
    567		/* generate an interrupt */
    568		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
    569		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
    570	}
    571}
    572
    573
    574/**
    575 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
    576 *
    577 * @adev: amdgpu_device pointer
    578 *
    579 * Stop the gfx async dma ring buffers (NAVI10).
    580 */
    581static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
    582{
    583	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
    584	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
    585	u32 rb_cntl, ib_cntl;
    586	int i;
    587
    588	if ((adev->mman.buffer_funcs_ring == sdma0) ||
    589	    (adev->mman.buffer_funcs_ring == sdma1))
    590		amdgpu_ttm_set_buffer_funcs_status(adev, false);
    591
    592	for (i = 0; i < adev->sdma.num_instances; i++) {
    593		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
    594		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
    595		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
    596		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
    597		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
    598		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
    599	}
    600}
    601
    602/**
    603 * sdma_v5_0_rlc_stop - stop the compute async dma engines
    604 *
    605 * @adev: amdgpu_device pointer
    606 *
    607 * Stop the compute async dma queues (NAVI10).
    608 */
    609static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
    610{
    611	/* XXX todo */
    612}
    613
    614/**
    615 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
    616 *
    617 * @adev: amdgpu_device pointer
    618 * @enable: enable/disable the DMA MEs context switch.
    619 *
    620 * Halt or unhalt the async dma engines context switch (NAVI10).
    621 */
    622static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
    623{
    624	u32 f32_cntl = 0, phase_quantum = 0;
    625	int i;
    626
    627	if (amdgpu_sdma_phase_quantum) {
    628		unsigned value = amdgpu_sdma_phase_quantum;
    629		unsigned unit = 0;
    630
    631		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
    632				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
    633			value = (value + 1) >> 1;
    634			unit++;
    635		}
    636		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
    637			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
    638			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
    639				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
    640			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
    641				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
    642			WARN_ONCE(1,
    643			"clamping sdma_phase_quantum to %uK clock cycles\n",
    644				  value << unit);
    645		}
    646		phase_quantum =
    647			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
    648			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
    649	}
    650
    651	for (i = 0; i < adev->sdma.num_instances; i++) {
    652		if (!amdgpu_sriov_vf(adev)) {
    653			f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
    654			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
    655						 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
    656		}
    657
    658		if (enable && amdgpu_sdma_phase_quantum) {
    659			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
    660			       phase_quantum);
    661			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
    662			       phase_quantum);
    663			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
    664			       phase_quantum);
    665		}
    666		if (!amdgpu_sriov_vf(adev))
    667			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
    668	}
    669
    670}
    671
    672/**
    673 * sdma_v5_0_enable - stop the async dma engines
    674 *
    675 * @adev: amdgpu_device pointer
    676 * @enable: enable/disable the DMA MEs.
    677 *
    678 * Halt or unhalt the async dma engines (NAVI10).
    679 */
    680static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
    681{
    682	u32 f32_cntl;
    683	int i;
    684
    685	if (!enable) {
    686		sdma_v5_0_gfx_stop(adev);
    687		sdma_v5_0_rlc_stop(adev);
    688	}
    689
    690	if (amdgpu_sriov_vf(adev))
    691		return;
    692
    693	for (i = 0; i < adev->sdma.num_instances; i++) {
    694		f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
    695		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
    696		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
    697	}
    698}
    699
    700/**
    701 * sdma_v5_0_gfx_resume - setup and start the async dma engines
    702 *
    703 * @adev: amdgpu_device pointer
    704 *
    705 * Set up the gfx DMA ring buffers and enable them (NAVI10).
    706 * Returns 0 for success, error for failure.
    707 */
    708static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
    709{
    710	struct amdgpu_ring *ring;
    711	u32 rb_cntl, ib_cntl;
    712	u32 rb_bufsz;
    713	u32 doorbell;
    714	u32 doorbell_offset;
    715	u32 temp;
    716	u32 wptr_poll_cntl;
    717	u64 wptr_gpu_addr;
    718	int i, r;
    719
    720	for (i = 0; i < adev->sdma.num_instances; i++) {
    721		ring = &adev->sdma.instance[i].ring;
    722
    723		if (!amdgpu_sriov_vf(adev))
    724			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
    725
    726		/* Set ring buffer size in dwords */
    727		rb_bufsz = order_base_2(ring->ring_size / 4);
    728		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
    729		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
    730#ifdef __BIG_ENDIAN
    731		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
    732		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
    733					RPTR_WRITEBACK_SWAP_ENABLE, 1);
    734#endif
    735		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
    736
    737		/* Initialize the ring buffer's read and write pointers */
    738		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
    739		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
    740		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
    741		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
    742
    743		/* setup the wptr shadow polling */
    744		wptr_gpu_addr = ring->wptr_gpu_addr;
    745		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
    746		       lower_32_bits(wptr_gpu_addr));
    747		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
    748		       upper_32_bits(wptr_gpu_addr));
    749		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
    750							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
    751		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
    752					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
    753					       F32_POLL_ENABLE, 1);
    754		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
    755		       wptr_poll_cntl);
    756
    757		/* set the wb address whether it's enabled or not */
    758		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
    759		       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
    760		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
    761		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
    762
    763		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
    764
    765		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
    766		       ring->gpu_addr >> 8);
    767		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
    768		       ring->gpu_addr >> 40);
    769
    770		ring->wptr = 0;
    771
    772		/* before programing wptr to a less value, need set minor_ptr_update first */
    773		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
    774
    775		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
    776			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
    777			       lower_32_bits(ring->wptr << 2));
    778			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
    779			       upper_32_bits(ring->wptr << 2));
    780		}
    781
    782		doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
    783		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
    784						mmSDMA0_GFX_DOORBELL_OFFSET));
    785
    786		if (ring->use_doorbell) {
    787			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
    788			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
    789					OFFSET, ring->doorbell_index);
    790		} else {
    791			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
    792		}
    793		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
    794		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
    795		       doorbell_offset);
    796
    797		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
    798						      ring->doorbell_index, 20);
    799
    800		if (amdgpu_sriov_vf(adev))
    801			sdma_v5_0_ring_set_wptr(ring);
    802
    803		/* set minor_ptr_update to 0 after wptr programed */
    804		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
    805
    806		if (!amdgpu_sriov_vf(adev)) {
    807			/* set utc l1 enable flag always to 1 */
    808			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
    809			temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
    810
    811			/* enable MCBP */
    812			temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
    813			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
    814
    815			/* Set up RESP_MODE to non-copy addresses */
    816			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
    817			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
    818			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
    819			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
    820
    821			/* program default cache read and write policy */
    822			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
    823			/* clean read policy and write policy bits */
    824			temp &= 0xFF0FFF;
    825			temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
    826			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
    827		}
    828
    829		if (!amdgpu_sriov_vf(adev)) {
    830			/* unhalt engine */
    831			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
    832			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
    833			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
    834		}
    835
    836		/* enable DMA RB */
    837		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
    838		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
    839
    840		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
    841		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
    842#ifdef __BIG_ENDIAN
    843		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
    844#endif
    845		/* enable DMA IBs */
    846		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
    847
    848		ring->sched.ready = true;
    849
    850		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
    851			sdma_v5_0_ctx_switch_enable(adev, true);
    852			sdma_v5_0_enable(adev, true);
    853		}
    854
    855		r = amdgpu_ring_test_helper(ring);
    856		if (r)
    857			return r;
    858
    859		if (adev->mman.buffer_funcs_ring == ring)
    860			amdgpu_ttm_set_buffer_funcs_status(adev, true);
    861	}
    862
    863	return 0;
    864}
    865
    866/**
    867 * sdma_v5_0_rlc_resume - setup and start the async dma engines
    868 *
    869 * @adev: amdgpu_device pointer
    870 *
    871 * Set up the compute DMA queues and enable them (NAVI10).
    872 * Returns 0 for success, error for failure.
    873 */
    874static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
    875{
    876	return 0;
    877}
    878
    879/**
    880 * sdma_v5_0_load_microcode - load the sDMA ME ucode
    881 *
    882 * @adev: amdgpu_device pointer
    883 *
    884 * Loads the sDMA0/1 ucode.
    885 * Returns 0 for success, -EINVAL if the ucode is not available.
    886 */
    887static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
    888{
    889	const struct sdma_firmware_header_v1_0 *hdr;
    890	const __le32 *fw_data;
    891	u32 fw_size;
    892	int i, j;
    893
    894	/* halt the MEs */
    895	sdma_v5_0_enable(adev, false);
    896
    897	for (i = 0; i < adev->sdma.num_instances; i++) {
    898		if (!adev->sdma.instance[i].fw)
    899			return -EINVAL;
    900
    901		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
    902		amdgpu_ucode_print_sdma_hdr(&hdr->header);
    903		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
    904
    905		fw_data = (const __le32 *)
    906			(adev->sdma.instance[i].fw->data +
    907				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
    908
    909		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
    910
    911		for (j = 0; j < fw_size; j++) {
    912			if (amdgpu_emu_mode == 1 && j % 500 == 0)
    913				msleep(1);
    914			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
    915		}
    916
    917		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
    918	}
    919
    920	return 0;
    921}
    922
    923/**
    924 * sdma_v5_0_start - setup and start the async dma engines
    925 *
    926 * @adev: amdgpu_device pointer
    927 *
    928 * Set up the DMA engines and enable them (NAVI10).
    929 * Returns 0 for success, error for failure.
    930 */
    931static int sdma_v5_0_start(struct amdgpu_device *adev)
    932{
    933	int r = 0;
    934
    935	if (amdgpu_sriov_vf(adev)) {
    936		sdma_v5_0_ctx_switch_enable(adev, false);
    937		sdma_v5_0_enable(adev, false);
    938
    939		/* set RB registers */
    940		r = sdma_v5_0_gfx_resume(adev);
    941		return r;
    942	}
    943
    944	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
    945		r = sdma_v5_0_load_microcode(adev);
    946		if (r)
    947			return r;
    948	}
    949
    950	/* unhalt the MEs */
    951	sdma_v5_0_enable(adev, true);
    952	/* enable sdma ring preemption */
    953	sdma_v5_0_ctx_switch_enable(adev, true);
    954
    955	/* start the gfx rings and rlc compute queues */
    956	r = sdma_v5_0_gfx_resume(adev);
    957	if (r)
    958		return r;
    959	r = sdma_v5_0_rlc_resume(adev);
    960
    961	return r;
    962}
    963
    964static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
    965			      struct amdgpu_mqd_prop *prop)
    966{
    967	struct v10_sdma_mqd *m = mqd;
    968	uint64_t wb_gpu_addr;
    969
    970	m->sdmax_rlcx_rb_cntl =
    971		order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
    972		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
    973		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
    974		1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
    975
    976	m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
    977	m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
    978
    979	m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
    980						  mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
    981
    982	wb_gpu_addr = prop->wptr_gpu_addr;
    983	m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
    984	m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
    985
    986	wb_gpu_addr = prop->rptr_gpu_addr;
    987	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
    988	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
    989
    990	m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
    991							mmSDMA0_GFX_IB_CNTL));
    992
    993	m->sdmax_rlcx_doorbell_offset =
    994		prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
    995
    996	m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
    997
    998	return 0;
    999}
   1000
   1001static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
   1002{
   1003	adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
   1004	adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
   1005}
   1006
   1007/**
   1008 * sdma_v5_0_ring_test_ring - simple async dma engine test
   1009 *
   1010 * @ring: amdgpu_ring structure holding ring information
   1011 *
   1012 * Test the DMA engine by writing using it to write an
   1013 * value to memory. (NAVI10).
   1014 * Returns 0 for success, error for failure.
   1015 */
   1016static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
   1017{
   1018	struct amdgpu_device *adev = ring->adev;
   1019	unsigned i;
   1020	unsigned index;
   1021	int r;
   1022	u32 tmp;
   1023	u64 gpu_addr;
   1024	volatile uint32_t *cpu_ptr = NULL;
   1025
   1026	tmp = 0xCAFEDEAD;
   1027
   1028	if (ring->is_mes_queue) {
   1029		uint32_t offset = 0;
   1030		offset = amdgpu_mes_ctx_get_offs(ring,
   1031					 AMDGPU_MES_CTX_PADDING_OFFS);
   1032		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
   1033		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
   1034		*cpu_ptr = tmp;
   1035	} else {
   1036		r = amdgpu_device_wb_get(adev, &index);
   1037		if (r) {
   1038			dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
   1039			return r;
   1040		}
   1041
   1042		gpu_addr = adev->wb.gpu_addr + (index * 4);
   1043		adev->wb.wb[index] = cpu_to_le32(tmp);
   1044	}
   1045
   1046	r = amdgpu_ring_alloc(ring, 20);
   1047	if (r) {
   1048		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
   1049		amdgpu_device_wb_free(adev, index);
   1050		return r;
   1051	}
   1052
   1053	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
   1054			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
   1055	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
   1056	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
   1057	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
   1058	amdgpu_ring_write(ring, 0xDEADBEEF);
   1059	amdgpu_ring_commit(ring);
   1060
   1061	for (i = 0; i < adev->usec_timeout; i++) {
   1062		if (ring->is_mes_queue)
   1063			tmp = le32_to_cpu(*cpu_ptr);
   1064		else
   1065			tmp = le32_to_cpu(adev->wb.wb[index]);
   1066		if (tmp == 0xDEADBEEF)
   1067			break;
   1068		if (amdgpu_emu_mode == 1)
   1069			msleep(1);
   1070		else
   1071			udelay(1);
   1072	}
   1073
   1074	if (i >= adev->usec_timeout)
   1075		r = -ETIMEDOUT;
   1076
   1077	if (!ring->is_mes_queue)
   1078		amdgpu_device_wb_free(adev, index);
   1079
   1080	return r;
   1081}
   1082
   1083/**
   1084 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
   1085 *
   1086 * @ring: amdgpu_ring structure holding ring information
   1087 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
   1088 *
   1089 * Test a simple IB in the DMA ring (NAVI10).
   1090 * Returns 0 on success, error on failure.
   1091 */
   1092static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
   1093{
   1094	struct amdgpu_device *adev = ring->adev;
   1095	struct amdgpu_ib ib;
   1096	struct dma_fence *f = NULL;
   1097	unsigned index;
   1098	long r;
   1099	u32 tmp = 0;
   1100	u64 gpu_addr;
   1101	volatile uint32_t *cpu_ptr = NULL;
   1102
   1103	tmp = 0xCAFEDEAD;
   1104	memset(&ib, 0, sizeof(ib));
   1105
   1106	if (ring->is_mes_queue) {
   1107		uint32_t offset = 0;
   1108		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
   1109		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
   1110		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
   1111
   1112		offset = amdgpu_mes_ctx_get_offs(ring,
   1113					 AMDGPU_MES_CTX_PADDING_OFFS);
   1114		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
   1115		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
   1116		*cpu_ptr = tmp;
   1117	} else {
   1118		r = amdgpu_device_wb_get(adev, &index);
   1119		if (r) {
   1120			dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
   1121			return r;
   1122		}
   1123
   1124		gpu_addr = adev->wb.gpu_addr + (index * 4);
   1125		adev->wb.wb[index] = cpu_to_le32(tmp);
   1126
   1127		r = amdgpu_ib_get(adev, NULL, 256,
   1128					AMDGPU_IB_POOL_DIRECT, &ib);
   1129		if (r) {
   1130			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
   1131			goto err0;
   1132		}
   1133	}
   1134
   1135	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
   1136		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
   1137	ib.ptr[1] = lower_32_bits(gpu_addr);
   1138	ib.ptr[2] = upper_32_bits(gpu_addr);
   1139	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
   1140	ib.ptr[4] = 0xDEADBEEF;
   1141	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
   1142	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
   1143	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
   1144	ib.length_dw = 8;
   1145
   1146	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
   1147	if (r)
   1148		goto err1;
   1149
   1150	r = dma_fence_wait_timeout(f, false, timeout);
   1151	if (r == 0) {
   1152		DRM_ERROR("amdgpu: IB test timed out\n");
   1153		r = -ETIMEDOUT;
   1154		goto err1;
   1155	} else if (r < 0) {
   1156		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
   1157		goto err1;
   1158	}
   1159
   1160	if (ring->is_mes_queue)
   1161		tmp = le32_to_cpu(*cpu_ptr);
   1162	else
   1163		tmp = le32_to_cpu(adev->wb.wb[index]);
   1164
   1165	if (tmp == 0xDEADBEEF)
   1166		r = 0;
   1167	else
   1168		r = -EINVAL;
   1169
   1170err1:
   1171	amdgpu_ib_free(adev, &ib, NULL);
   1172	dma_fence_put(f);
   1173err0:
   1174	if (!ring->is_mes_queue)
   1175		amdgpu_device_wb_free(adev, index);
   1176	return r;
   1177}
   1178
   1179
   1180/**
   1181 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
   1182 *
   1183 * @ib: indirect buffer to fill with commands
   1184 * @pe: addr of the page entry
   1185 * @src: src addr to copy from
   1186 * @count: number of page entries to update
   1187 *
   1188 * Update PTEs by copying them from the GART using sDMA (NAVI10).
   1189 */
   1190static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
   1191				  uint64_t pe, uint64_t src,
   1192				  unsigned count)
   1193{
   1194	unsigned bytes = count * 8;
   1195
   1196	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
   1197		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
   1198	ib->ptr[ib->length_dw++] = bytes - 1;
   1199	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
   1200	ib->ptr[ib->length_dw++] = lower_32_bits(src);
   1201	ib->ptr[ib->length_dw++] = upper_32_bits(src);
   1202	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
   1203	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
   1204
   1205}
   1206
   1207/**
   1208 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
   1209 *
   1210 * @ib: indirect buffer to fill with commands
   1211 * @pe: addr of the page entry
   1212 * @value: dst addr to write into pe
   1213 * @count: number of page entries to update
   1214 * @incr: increase next addr by incr bytes
   1215 *
   1216 * Update PTEs by writing them manually using sDMA (NAVI10).
   1217 */
   1218static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
   1219				   uint64_t value, unsigned count,
   1220				   uint32_t incr)
   1221{
   1222	unsigned ndw = count * 2;
   1223
   1224	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
   1225		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
   1226	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
   1227	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
   1228	ib->ptr[ib->length_dw++] = ndw - 1;
   1229	for (; ndw > 0; ndw -= 2) {
   1230		ib->ptr[ib->length_dw++] = lower_32_bits(value);
   1231		ib->ptr[ib->length_dw++] = upper_32_bits(value);
   1232		value += incr;
   1233	}
   1234}
   1235
   1236/**
   1237 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
   1238 *
   1239 * @ib: indirect buffer to fill with commands
   1240 * @pe: addr of the page entry
   1241 * @addr: dst addr to write into pe
   1242 * @count: number of page entries to update
   1243 * @incr: increase next addr by incr bytes
   1244 * @flags: access flags
   1245 *
   1246 * Update the page tables using sDMA (NAVI10).
   1247 */
   1248static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
   1249				     uint64_t pe,
   1250				     uint64_t addr, unsigned count,
   1251				     uint32_t incr, uint64_t flags)
   1252{
   1253	/* for physically contiguous pages (vram) */
   1254	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
   1255	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
   1256	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
   1257	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
   1258	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
   1259	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
   1260	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
   1261	ib->ptr[ib->length_dw++] = incr; /* increment size */
   1262	ib->ptr[ib->length_dw++] = 0;
   1263	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
   1264}
   1265
   1266/**
   1267 * sdma_v5_0_ring_pad_ib - pad the IB
   1268 * @ring: amdgpu_ring structure holding ring information
   1269 * @ib: indirect buffer to fill with padding
   1270 *
   1271 * Pad the IB with NOPs to a boundary multiple of 8.
   1272 */
   1273static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
   1274{
   1275	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
   1276	u32 pad_count;
   1277	int i;
   1278
   1279	pad_count = (-ib->length_dw) & 0x7;
   1280	for (i = 0; i < pad_count; i++)
   1281		if (sdma && sdma->burst_nop && (i == 0))
   1282			ib->ptr[ib->length_dw++] =
   1283				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
   1284				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
   1285		else
   1286			ib->ptr[ib->length_dw++] =
   1287				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
   1288}
   1289
   1290
   1291/**
   1292 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
   1293 *
   1294 * @ring: amdgpu_ring pointer
   1295 *
   1296 * Make sure all previous operations are completed (CIK).
   1297 */
   1298static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
   1299{
   1300	uint32_t seq = ring->fence_drv.sync_seq;
   1301	uint64_t addr = ring->fence_drv.gpu_addr;
   1302
   1303	/* wait for idle */
   1304	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
   1305			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
   1306			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
   1307			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
   1308	amdgpu_ring_write(ring, addr & 0xfffffffc);
   1309	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
   1310	amdgpu_ring_write(ring, seq); /* reference */
   1311	amdgpu_ring_write(ring, 0xffffffff); /* mask */
   1312	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
   1313			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
   1314}
   1315
   1316
   1317/**
   1318 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
   1319 *
   1320 * @ring: amdgpu_ring pointer
   1321 * @vmid: vmid number to use
   1322 * @pd_addr: address
   1323 *
   1324 * Update the page table base and flush the VM TLB
   1325 * using sDMA (NAVI10).
   1326 */
   1327static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
   1328					 unsigned vmid, uint64_t pd_addr)
   1329{
   1330	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
   1331}
   1332
   1333static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
   1334				     uint32_t reg, uint32_t val)
   1335{
   1336	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
   1337			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
   1338	amdgpu_ring_write(ring, reg);
   1339	amdgpu_ring_write(ring, val);
   1340}
   1341
   1342static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
   1343					 uint32_t val, uint32_t mask)
   1344{
   1345	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
   1346			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
   1347			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
   1348	amdgpu_ring_write(ring, reg << 2);
   1349	amdgpu_ring_write(ring, 0);
   1350	amdgpu_ring_write(ring, val); /* reference */
   1351	amdgpu_ring_write(ring, mask); /* mask */
   1352	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
   1353			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
   1354}
   1355
   1356static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
   1357						   uint32_t reg0, uint32_t reg1,
   1358						   uint32_t ref, uint32_t mask)
   1359{
   1360	amdgpu_ring_emit_wreg(ring, reg0, ref);
   1361	/* wait for a cycle to reset vm_inv_eng*_ack */
   1362	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
   1363	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
   1364}
   1365
   1366static int sdma_v5_0_early_init(void *handle)
   1367{
   1368	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1369
   1370	sdma_v5_0_set_ring_funcs(adev);
   1371	sdma_v5_0_set_buffer_funcs(adev);
   1372	sdma_v5_0_set_vm_pte_funcs(adev);
   1373	sdma_v5_0_set_irq_funcs(adev);
   1374	sdma_v5_0_set_mqd_funcs(adev);
   1375
   1376	return 0;
   1377}
   1378
   1379
   1380static int sdma_v5_0_sw_init(void *handle)
   1381{
   1382	struct amdgpu_ring *ring;
   1383	int r, i;
   1384	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1385
   1386	/* SDMA trap event */
   1387	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
   1388			      SDMA0_5_0__SRCID__SDMA_TRAP,
   1389			      &adev->sdma.trap_irq);
   1390	if (r)
   1391		return r;
   1392
   1393	/* SDMA trap event */
   1394	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
   1395			      SDMA1_5_0__SRCID__SDMA_TRAP,
   1396			      &adev->sdma.trap_irq);
   1397	if (r)
   1398		return r;
   1399
   1400	r = sdma_v5_0_init_microcode(adev);
   1401	if (r) {
   1402		DRM_ERROR("Failed to load sdma firmware!\n");
   1403		return r;
   1404	}
   1405
   1406	for (i = 0; i < adev->sdma.num_instances; i++) {
   1407		ring = &adev->sdma.instance[i].ring;
   1408		ring->ring_obj = NULL;
   1409		ring->use_doorbell = true;
   1410
   1411		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
   1412				ring->use_doorbell?"true":"false");
   1413
   1414		ring->doorbell_index = (i == 0) ?
   1415			(adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
   1416			: (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
   1417
   1418		sprintf(ring->name, "sdma%d", i);
   1419		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
   1420				     (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
   1421				     AMDGPU_SDMA_IRQ_INSTANCE1,
   1422				     AMDGPU_RING_PRIO_DEFAULT, NULL);
   1423		if (r)
   1424			return r;
   1425	}
   1426
   1427	return r;
   1428}
   1429
   1430static int sdma_v5_0_sw_fini(void *handle)
   1431{
   1432	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1433	int i;
   1434
   1435	for (i = 0; i < adev->sdma.num_instances; i++) {
   1436		release_firmware(adev->sdma.instance[i].fw);
   1437		adev->sdma.instance[i].fw = NULL;
   1438
   1439		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
   1440	}
   1441
   1442	return 0;
   1443}
   1444
   1445static int sdma_v5_0_hw_init(void *handle)
   1446{
   1447	int r;
   1448	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1449
   1450	sdma_v5_0_init_golden_registers(adev);
   1451
   1452	r = sdma_v5_0_start(adev);
   1453
   1454	return r;
   1455}
   1456
   1457static int sdma_v5_0_hw_fini(void *handle)
   1458{
   1459	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1460
   1461	if (amdgpu_sriov_vf(adev))
   1462		return 0;
   1463
   1464	sdma_v5_0_ctx_switch_enable(adev, false);
   1465	sdma_v5_0_enable(adev, false);
   1466
   1467	return 0;
   1468}
   1469
   1470static int sdma_v5_0_suspend(void *handle)
   1471{
   1472	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1473
   1474	return sdma_v5_0_hw_fini(adev);
   1475}
   1476
   1477static int sdma_v5_0_resume(void *handle)
   1478{
   1479	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1480
   1481	return sdma_v5_0_hw_init(adev);
   1482}
   1483
   1484static bool sdma_v5_0_is_idle(void *handle)
   1485{
   1486	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1487	u32 i;
   1488
   1489	for (i = 0; i < adev->sdma.num_instances; i++) {
   1490		u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
   1491
   1492		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
   1493			return false;
   1494	}
   1495
   1496	return true;
   1497}
   1498
   1499static int sdma_v5_0_wait_for_idle(void *handle)
   1500{
   1501	unsigned i;
   1502	u32 sdma0, sdma1;
   1503	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1504
   1505	for (i = 0; i < adev->usec_timeout; i++) {
   1506		sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
   1507		sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
   1508
   1509		if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
   1510			return 0;
   1511		udelay(1);
   1512	}
   1513	return -ETIMEDOUT;
   1514}
   1515
   1516static int sdma_v5_0_soft_reset(void *handle)
   1517{
   1518	/* todo */
   1519
   1520	return 0;
   1521}
   1522
   1523static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
   1524{
   1525	int i, r = 0;
   1526	struct amdgpu_device *adev = ring->adev;
   1527	u32 index = 0;
   1528	u64 sdma_gfx_preempt;
   1529
   1530	amdgpu_sdma_get_index_from_ring(ring, &index);
   1531	if (index == 0)
   1532		sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
   1533	else
   1534		sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
   1535
   1536	/* assert preemption condition */
   1537	amdgpu_ring_set_preempt_cond_exec(ring, false);
   1538
   1539	/* emit the trailing fence */
   1540	ring->trail_seq += 1;
   1541	amdgpu_ring_alloc(ring, 10);
   1542	sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
   1543				  ring->trail_seq, 0);
   1544	amdgpu_ring_commit(ring);
   1545
   1546	/* assert IB preemption */
   1547	WREG32(sdma_gfx_preempt, 1);
   1548
   1549	/* poll the trailing fence */
   1550	for (i = 0; i < adev->usec_timeout; i++) {
   1551		if (ring->trail_seq ==
   1552		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
   1553			break;
   1554		udelay(1);
   1555	}
   1556
   1557	if (i >= adev->usec_timeout) {
   1558		r = -EINVAL;
   1559		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
   1560	}
   1561
   1562	/* deassert IB preemption */
   1563	WREG32(sdma_gfx_preempt, 0);
   1564
   1565	/* deassert the preemption condition */
   1566	amdgpu_ring_set_preempt_cond_exec(ring, true);
   1567	return r;
   1568}
   1569
   1570static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
   1571					struct amdgpu_irq_src *source,
   1572					unsigned type,
   1573					enum amdgpu_interrupt_state state)
   1574{
   1575	u32 sdma_cntl;
   1576
   1577	if (!amdgpu_sriov_vf(adev)) {
   1578		u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
   1579			sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
   1580			sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
   1581
   1582		sdma_cntl = RREG32(reg_offset);
   1583		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
   1584					  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
   1585		WREG32(reg_offset, sdma_cntl);
   1586	}
   1587
   1588	return 0;
   1589}
   1590
   1591static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
   1592				      struct amdgpu_irq_src *source,
   1593				      struct amdgpu_iv_entry *entry)
   1594{
   1595	uint32_t mes_queue_id = entry->src_data[0];
   1596
   1597	DRM_DEBUG("IH: SDMA trap\n");
   1598
   1599	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
   1600		struct amdgpu_mes_queue *queue;
   1601
   1602		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
   1603
   1604		spin_lock(&adev->mes.queue_id_lock);
   1605		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
   1606		if (queue) {
   1607			DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
   1608			amdgpu_fence_process(queue->ring);
   1609		}
   1610		spin_unlock(&adev->mes.queue_id_lock);
   1611		return 0;
   1612	}
   1613
   1614	switch (entry->client_id) {
   1615	case SOC15_IH_CLIENTID_SDMA0:
   1616		switch (entry->ring_id) {
   1617		case 0:
   1618			amdgpu_fence_process(&adev->sdma.instance[0].ring);
   1619			break;
   1620		case 1:
   1621			/* XXX compute */
   1622			break;
   1623		case 2:
   1624			/* XXX compute */
   1625			break;
   1626		case 3:
   1627			/* XXX page queue*/
   1628			break;
   1629		}
   1630		break;
   1631	case SOC15_IH_CLIENTID_SDMA1:
   1632		switch (entry->ring_id) {
   1633		case 0:
   1634			amdgpu_fence_process(&adev->sdma.instance[1].ring);
   1635			break;
   1636		case 1:
   1637			/* XXX compute */
   1638			break;
   1639		case 2:
   1640			/* XXX compute */
   1641			break;
   1642		case 3:
   1643			/* XXX page queue*/
   1644			break;
   1645		}
   1646		break;
   1647	}
   1648	return 0;
   1649}
   1650
   1651static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
   1652					      struct amdgpu_irq_src *source,
   1653					      struct amdgpu_iv_entry *entry)
   1654{
   1655	return 0;
   1656}
   1657
   1658static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
   1659						       bool enable)
   1660{
   1661	uint32_t data, def;
   1662	int i;
   1663
   1664	for (i = 0; i < adev->sdma.num_instances; i++) {
   1665		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
   1666			/* Enable sdma clock gating */
   1667			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
   1668			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
   1669				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
   1670				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
   1671				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
   1672				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
   1673				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
   1674				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
   1675				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
   1676			if (def != data)
   1677				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
   1678		} else {
   1679			/* Disable sdma clock gating */
   1680			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
   1681			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
   1682				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
   1683				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
   1684				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
   1685				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
   1686				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
   1687				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
   1688				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
   1689			if (def != data)
   1690				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
   1691		}
   1692	}
   1693}
   1694
   1695static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
   1696						      bool enable)
   1697{
   1698	uint32_t data, def;
   1699	int i;
   1700
   1701	for (i = 0; i < adev->sdma.num_instances; i++) {
   1702		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
   1703			/* Enable sdma mem light sleep */
   1704			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
   1705			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
   1706			if (def != data)
   1707				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
   1708
   1709		} else {
   1710			/* Disable sdma mem light sleep */
   1711			def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
   1712			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
   1713			if (def != data)
   1714				WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
   1715
   1716		}
   1717	}
   1718}
   1719
   1720static int sdma_v5_0_set_clockgating_state(void *handle,
   1721					   enum amd_clockgating_state state)
   1722{
   1723	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1724
   1725	if (amdgpu_sriov_vf(adev))
   1726		return 0;
   1727
   1728	switch (adev->ip_versions[SDMA0_HWIP][0]) {
   1729	case IP_VERSION(5, 0, 0):
   1730	case IP_VERSION(5, 0, 2):
   1731	case IP_VERSION(5, 0, 5):
   1732		sdma_v5_0_update_medium_grain_clock_gating(adev,
   1733				state == AMD_CG_STATE_GATE);
   1734		sdma_v5_0_update_medium_grain_light_sleep(adev,
   1735				state == AMD_CG_STATE_GATE);
   1736		break;
   1737	default:
   1738		break;
   1739	}
   1740
   1741	return 0;
   1742}
   1743
   1744static int sdma_v5_0_set_powergating_state(void *handle,
   1745					  enum amd_powergating_state state)
   1746{
   1747	return 0;
   1748}
   1749
   1750static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
   1751{
   1752	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   1753	int data;
   1754
   1755	if (amdgpu_sriov_vf(adev))
   1756		*flags = 0;
   1757
   1758	/* AMD_CG_SUPPORT_SDMA_MGCG */
   1759	data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
   1760	if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
   1761		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
   1762
   1763	/* AMD_CG_SUPPORT_SDMA_LS */
   1764	data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
   1765	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
   1766		*flags |= AMD_CG_SUPPORT_SDMA_LS;
   1767}
   1768
   1769const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
   1770	.name = "sdma_v5_0",
   1771	.early_init = sdma_v5_0_early_init,
   1772	.late_init = NULL,
   1773	.sw_init = sdma_v5_0_sw_init,
   1774	.sw_fini = sdma_v5_0_sw_fini,
   1775	.hw_init = sdma_v5_0_hw_init,
   1776	.hw_fini = sdma_v5_0_hw_fini,
   1777	.suspend = sdma_v5_0_suspend,
   1778	.resume = sdma_v5_0_resume,
   1779	.is_idle = sdma_v5_0_is_idle,
   1780	.wait_for_idle = sdma_v5_0_wait_for_idle,
   1781	.soft_reset = sdma_v5_0_soft_reset,
   1782	.set_clockgating_state = sdma_v5_0_set_clockgating_state,
   1783	.set_powergating_state = sdma_v5_0_set_powergating_state,
   1784	.get_clockgating_state = sdma_v5_0_get_clockgating_state,
   1785};
   1786
   1787static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
   1788	.type = AMDGPU_RING_TYPE_SDMA,
   1789	.align_mask = 0xf,
   1790	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
   1791	.support_64bit_ptrs = true,
   1792	.secure_submission_supported = true,
   1793	.vmhub = AMDGPU_GFXHUB_0,
   1794	.get_rptr = sdma_v5_0_ring_get_rptr,
   1795	.get_wptr = sdma_v5_0_ring_get_wptr,
   1796	.set_wptr = sdma_v5_0_ring_set_wptr,
   1797	.emit_frame_size =
   1798		5 + /* sdma_v5_0_ring_init_cond_exec */
   1799		6 + /* sdma_v5_0_ring_emit_hdp_flush */
   1800		3 + /* hdp_invalidate */
   1801		6 + /* sdma_v5_0_ring_emit_pipeline_sync */
   1802		/* sdma_v5_0_ring_emit_vm_flush */
   1803		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
   1804		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
   1805		10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
   1806	.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
   1807	.emit_ib = sdma_v5_0_ring_emit_ib,
   1808	.emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
   1809	.emit_fence = sdma_v5_0_ring_emit_fence,
   1810	.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
   1811	.emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
   1812	.emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
   1813	.test_ring = sdma_v5_0_ring_test_ring,
   1814	.test_ib = sdma_v5_0_ring_test_ib,
   1815	.insert_nop = sdma_v5_0_ring_insert_nop,
   1816	.pad_ib = sdma_v5_0_ring_pad_ib,
   1817	.emit_wreg = sdma_v5_0_ring_emit_wreg,
   1818	.emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
   1819	.emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
   1820	.init_cond_exec = sdma_v5_0_ring_init_cond_exec,
   1821	.patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
   1822	.preempt_ib = sdma_v5_0_ring_preempt_ib,
   1823};
   1824
   1825static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
   1826{
   1827	int i;
   1828
   1829	for (i = 0; i < adev->sdma.num_instances; i++) {
   1830		adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
   1831		adev->sdma.instance[i].ring.me = i;
   1832	}
   1833}
   1834
   1835static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
   1836	.set = sdma_v5_0_set_trap_irq_state,
   1837	.process = sdma_v5_0_process_trap_irq,
   1838};
   1839
   1840static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
   1841	.process = sdma_v5_0_process_illegal_inst_irq,
   1842};
   1843
   1844static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
   1845{
   1846	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
   1847					adev->sdma.num_instances;
   1848	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
   1849	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
   1850}
   1851
   1852/**
   1853 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
   1854 *
   1855 * @ib: indirect buffer to copy to
   1856 * @src_offset: src GPU address
   1857 * @dst_offset: dst GPU address
   1858 * @byte_count: number of bytes to xfer
   1859 * @tmz: if a secure copy should be used
   1860 *
   1861 * Copy GPU buffers using the DMA engine (NAVI10).
   1862 * Used by the amdgpu ttm implementation to move pages if
   1863 * registered as the asic copy callback.
   1864 */
   1865static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
   1866				       uint64_t src_offset,
   1867				       uint64_t dst_offset,
   1868				       uint32_t byte_count,
   1869				       bool tmz)
   1870{
   1871	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
   1872		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
   1873		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
   1874	ib->ptr[ib->length_dw++] = byte_count - 1;
   1875	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
   1876	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
   1877	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
   1878	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
   1879	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
   1880}
   1881
   1882/**
   1883 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
   1884 *
   1885 * @ib: indirect buffer to fill
   1886 * @src_data: value to write to buffer
   1887 * @dst_offset: dst GPU address
   1888 * @byte_count: number of bytes to xfer
   1889 *
   1890 * Fill GPU buffers using the DMA engine (NAVI10).
   1891 */
   1892static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
   1893				       uint32_t src_data,
   1894				       uint64_t dst_offset,
   1895				       uint32_t byte_count)
   1896{
   1897	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
   1898	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
   1899	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
   1900	ib->ptr[ib->length_dw++] = src_data;
   1901	ib->ptr[ib->length_dw++] = byte_count - 1;
   1902}
   1903
   1904static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
   1905	.copy_max_bytes = 0x400000,
   1906	.copy_num_dw = 7,
   1907	.emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
   1908
   1909	.fill_max_bytes = 0x400000,
   1910	.fill_num_dw = 5,
   1911	.emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
   1912};
   1913
   1914static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
   1915{
   1916	if (adev->mman.buffer_funcs == NULL) {
   1917		adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
   1918		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
   1919	}
   1920}
   1921
   1922static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
   1923	.copy_pte_num_dw = 7,
   1924	.copy_pte = sdma_v5_0_vm_copy_pte,
   1925	.write_pte = sdma_v5_0_vm_write_pte,
   1926	.set_pte_pde = sdma_v5_0_vm_set_pte_pde,
   1927};
   1928
   1929static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
   1930{
   1931	unsigned i;
   1932
   1933	if (adev->vm_manager.vm_pte_funcs == NULL) {
   1934		adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
   1935		for (i = 0; i < adev->sdma.num_instances; i++) {
   1936			adev->vm_manager.vm_pte_scheds[i] =
   1937				&adev->sdma.instance[i].ring.sched;
   1938		}
   1939		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
   1940	}
   1941}
   1942
   1943const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
   1944	.type = AMD_IP_BLOCK_TYPE_SDMA,
   1945	.major = 5,
   1946	.minor = 0,
   1947	.rev = 0,
   1948	.funcs = &sdma_v5_0_ip_funcs,
   1949};