cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

smuio_v13_0.c (4267B)

      1/*
      2 * Copyright 2020 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23#include "amdgpu.h"
     24#include "smuio_v13_0.h"
     25#include "smuio/smuio_13_0_2_offset.h"
     26#include "smuio/smuio_13_0_2_sh_mask.h"
     27
     28#define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK	0x00000001L
     29
     30static u32 smuio_v13_0_get_rom_index_offset(struct amdgpu_device *adev)
     31{
     32	return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
     33}
     34
     35static u32 smuio_v13_0_get_rom_data_offset(struct amdgpu_device *adev)
     36{
     37	return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
     38}
     39
     40static void smuio_v13_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
     41{
     42	u32 def, data;
     43
     44	/* enable/disable ROM CG is not supported on APU */
     45	if (adev->flags & AMD_IS_APU)
     46		return;
     47
     48	def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
     49
     50	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
     51		data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
     52			CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
     53	else
     54		data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
     55			CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
     56
     57	if (def != data)
     58		WREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0, data);
     59}
     60
     61static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
     62{
     63	u32 data;
     64
     65	/* CGTT_ROM_CLK_CTRL0 is not available for APU */
     66	if (adev->flags & AMD_IS_APU)
     67		return;
     68
     69	data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
     70	if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
     71		*flags |= AMD_CG_SUPPORT_ROM_MGCG;
     72}
     73
     74/**
     75 * smuio_v13_0_get_die_id - query die id from FCH.
     76 *
     77 * @adev: amdgpu device pointer
     78 *
     79 * Returns die id
     80 */
     81static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev)
     82{
     83	u32 data, die_id;
     84
     85	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
     86	die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);
     87
     88	return die_id;
     89}
     90
     91/**
     92 * smuio_v13_0_get_socket_id - query socket id from FCH
     93 *
     94 * @adev: amdgpu device pointer
     95 *
     96 * Returns socket id
     97 */
     98static u32 smuio_v13_0_get_socket_id(struct amdgpu_device *adev)
     99{
    100	u32 data, socket_id;
    101
    102	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
    103	socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
    104
    105	return socket_id;
    106}
    107
    108/**
    109 * smuio_v13_0_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s.
    110 *
    111 * @adev: amdgpu device pointer
    112 *
    113 * Returns true on success or false otherwise.
    114 */
    115static bool smuio_v13_0_is_host_gpu_xgmi_supported(struct amdgpu_device *adev)
    116{
    117	u32 data;
    118
    119	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
    120	data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID);
    121	/* data[4:0]
    122	 * bit 0 == 0 host-gpu interface is PCIE
    123	 * bit 0 == 1 host-gpu interface is Alternate Protocal
    124	 * for AMD, this is XGMI
    125	 */
    126	data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK;
    127
    128	return data ? true : false;
    129}
    130
    131const struct amdgpu_smuio_funcs smuio_v13_0_funcs = {
    132	.get_rom_index_offset = smuio_v13_0_get_rom_index_offset,
    133	.get_rom_data_offset = smuio_v13_0_get_rom_data_offset,
    134	.get_die_id = smuio_v13_0_get_die_id,
    135	.get_socket_id = smuio_v13_0_get_socket_id,
    136	.is_host_gpu_xgmi_supported = smuio_v13_0_is_host_gpu_xgmi_supported,
    137	.update_rom_clock_gating = smuio_v13_0_update_rom_clock_gating,
    138	.get_clock_gating_state = smuio_v13_0_get_clock_gating_state,
    139};