cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

umc_v6_1.h (2198B)

      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23#ifndef __UMC_V6_1_H__
     24#define __UMC_V6_1_H__
     25
     26#include "soc15_common.h"
     27#include "amdgpu.h"
     28
     29/* HBM  Memory Channel Width */
     30#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH	128
     31/* number of umc channel instance with memory map register access */
     32#define UMC_V6_1_CHANNEL_INSTANCE_NUM		4
     33/* number of umc instance with memory map register access */
     34#define UMC_V6_1_UMC_INSTANCE_NUM		8
     35/* total channel instances in one umc block */
     36#define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
     37/* UMC regiser per channel offset */
     38#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20	0x800
     39#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT	0x400
     40
     41/* EccErrCnt max value */
     42#define UMC_V6_1_CE_CNT_MAX		0xffff
     43/* umc ce interrupt threshold */
     44#define UMC_V6_1_CE_INT_THRESHOLD	0xffff
     45/* umc ce count initial value */
     46#define UMC_V6_1_CE_CNT_INIT	(UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
     47
     48extern struct amdgpu_umc_ras umc_v6_1_ras;
     49extern const uint32_t
     50	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
     51
     52#endif