cwsr_trap_handler_gfx9.asm (45239B)
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * gfx9: 26 * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3 27 * sp3 gfx9.sp3 -hex gfx9.hex 28 * 29 * arcturus: 30 * cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3 31 * sp3 arcturus.sp3 -hex arcturus.hex 32 * 33 * aldebaran: 34 * cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3 35 * sp3 aldebaran.sp3 -hex aldebaran.hex 36 */ 37 38#define CHIP_VEGAM 18 39#define CHIP_ARCTURUS 23 40#define CHIP_ALDEBARAN 25 41 42var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 43var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger 44var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 45 46/**************************************************************************/ 47/* variables */ 48/**************************************************************************/ 49var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 50var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 51var SQ_WAVE_STATUS_HALT_MASK = 0x2000 52var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 53var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 54var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 55var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 56var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 57var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 58 59var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 60var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 61var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 62var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 63var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 64 65#if ASIC_FAMILY >= CHIP_ALDEBARAN 66var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 6 67var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT = 12 68var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE = 6 69#else 70var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 71#endif 72 73var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 74var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 75var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 76var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 77var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 78var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 79var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 80var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 81var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 82var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 83var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 84var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 85var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 86var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 87var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 88var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 89 90var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 91var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 92 93var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 94var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 95 96var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 97 98var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 99var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 100var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 101var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 102 103/* Save */ 104var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 105var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 106var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 107var S_SAVE_PC_HI_HT_MASK = 0x01000000 108var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 109var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 110 111var s_save_spi_init_lo = exec_lo 112var s_save_spi_init_hi = exec_hi 113 114var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 115var s_save_pc_hi = ttmp1 116var s_save_exec_lo = ttmp2 117var s_save_exec_hi = ttmp3 118var s_save_tmp = ttmp14 119var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine 120var s_save_xnack_mask_lo = ttmp6 121var s_save_xnack_mask_hi = ttmp7 122var s_save_buf_rsrc0 = ttmp8 123var s_save_buf_rsrc1 = ttmp9 124var s_save_buf_rsrc2 = ttmp10 125var s_save_buf_rsrc3 = ttmp11 126var s_save_status = ttmp12 127var s_save_mem_offset = ttmp4 128var s_save_alloc_size = s_save_trapsts //conflict 129var s_save_m0 = ttmp5 130var s_save_ttmps_lo = s_save_tmp //no conflict 131var s_save_ttmps_hi = s_save_trapsts //no conflict 132 133/* Restore */ 134var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 135var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 136 137var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 138var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 139 140var s_restore_spi_init_lo = exec_lo 141var s_restore_spi_init_hi = exec_hi 142 143var s_restore_mem_offset = ttmp12 144var s_restore_tmp2 = ttmp13 145var s_restore_alloc_size = ttmp3 146var s_restore_tmp = ttmp2 147var s_restore_mem_offset_save = s_restore_tmp //no conflict 148var s_restore_accvgpr_offset_save = ttmp7 149 150var s_restore_m0 = s_restore_alloc_size //no conflict 151 152var s_restore_mode = s_restore_accvgpr_offset_save 153 154var s_restore_pc_lo = ttmp0 155var s_restore_pc_hi = ttmp1 156var s_restore_exec_lo = ttmp4 157var s_restore_exec_hi = ttmp5 158var s_restore_status = ttmp14 159var s_restore_trapsts = ttmp15 160var s_restore_xnack_mask_lo = xnack_mask_lo 161var s_restore_xnack_mask_hi = xnack_mask_hi 162var s_restore_buf_rsrc0 = ttmp8 163var s_restore_buf_rsrc1 = ttmp9 164var s_restore_buf_rsrc2 = ttmp10 165var s_restore_buf_rsrc3 = ttmp11 166var s_restore_ttmps_lo = s_restore_tmp //no conflict 167var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 168 169/**************************************************************************/ 170/* trap handler entry points */ 171/**************************************************************************/ 172/* Shader Main*/ 173 174shader main 175 asic(DEFAULT) 176 type(CS) 177 178 179 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 180 181L_JUMP_TO_RESTORE: 182 s_branch L_RESTORE //restore 183 184L_SKIP_RESTORE: 185 186 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 187 188 // Clear SPI_PRIO: do not save with elevated priority. 189 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 190 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 191 192 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 193 194 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 195 s_cbranch_scc0 L_NOT_HALTED 196 197L_HALTED: 198 // Host trap may occur while wave is halted. 199 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 200 s_cbranch_scc1 L_FETCH_2ND_TRAP 201 202L_CHECK_SAVE: 203 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 204 s_cbranch_scc1 L_SAVE //this is the operation for save 205 206 // Wave is halted but neither host trap nor SAVECTX is raised. 207 // Caused by instruction fetch memory violation. 208 // Spin wait until context saved to prevent interrupt storm. 209 s_sleep 0x10 210 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 211 s_branch L_CHECK_SAVE 212 213L_NOT_HALTED: 214 // Let second-level handle non-SAVECTX exception or trap. 215 // Any concurrent SAVECTX will be handled upon re-entry once halted. 216 217 // Check non-maskable exceptions. memory_violation, illegal_instruction 218 // and xnack_error exceptions always cause the wave to enter the trap 219 // handler. 220 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 221 s_cbranch_scc1 L_FETCH_2ND_TRAP 222 223 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 224 // Maskable exceptions only cause the wave to enter the trap handler if 225 // their respective bit in mode.excp_en is set. 226 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 227 s_cbranch_scc0 L_CHECK_TRAP_ID 228 229 s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 230 s_cbranch_scc0 L_NOT_ADDR_WATCH 231 s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 232 233L_NOT_ADDR_WATCH: 234 s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 235 s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 236 s_and_b32 ttmp2, ttmp2, ttmp3 237 s_cbranch_scc1 L_FETCH_2ND_TRAP 238 239L_CHECK_TRAP_ID: 240 // Check trap_id != 0 241 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 242 s_cbranch_scc1 L_FETCH_2ND_TRAP 243 244if SINGLE_STEP_MISSED_WORKAROUND 245 // Prioritize single step exception over context save. 246 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 247 s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 248 s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 249 s_cbranch_scc1 L_FETCH_2ND_TRAP 250end 251 252 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 253 s_cbranch_scc1 L_SAVE 254 255L_FETCH_2ND_TRAP: 256 // Preserve and clear scalar XNACK state before issuing scalar reads. 257 save_and_clear_ib_sts(ttmp14) 258 259 // Read second-level TBA/TMA from first-level TMA and jump if available. 260 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 261 // ttmp12 holds SQ_WAVE_STATUS 262 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 263 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 264 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 265 266 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 267 s_waitcnt lgkmcnt(0) 268 s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 269 s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 270 s_or_b32 ttmp11, ttmp11, ttmp2 271 272 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 273 s_waitcnt lgkmcnt(0) 274 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 275 s_waitcnt lgkmcnt(0) 276 277 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 278 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 279 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 280 281L_NO_NEXT_TRAP: 282 // If not caused by trap then halt wave to prevent re-entry. 283 s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 284 s_cbranch_scc1 L_TRAP_CASE 285 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 286 287 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 288 // Rewind the PC to prevent this from occurring. 289 s_sub_u32 ttmp0, ttmp0, 0x8 290 s_subb_u32 ttmp1, ttmp1, 0x0 291 292 s_branch L_EXIT_TRAP 293 294L_TRAP_CASE: 295 // Host trap will not cause trap re-entry. 296 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 297 s_cbranch_scc1 L_EXIT_TRAP 298 299 // Advance past trap instruction to prevent re-entry. 300 s_add_u32 ttmp0, ttmp0, 0x4 301 s_addc_u32 ttmp1, ttmp1, 0x0 302 303L_EXIT_TRAP: 304 s_and_b32 ttmp1, ttmp1, 0xFFFF 305 306 restore_ib_sts(ttmp14) 307 308 // Restore SQ_WAVE_STATUS. 309 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 310 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 311 set_status_without_spi_prio(s_save_status, ttmp2) 312 313 s_rfe_b64 [ttmp0, ttmp1] 314 315 // ********* End handling of non-CWSR traps ******************* 316 317/**************************************************************************/ 318/* save routine */ 319/**************************************************************************/ 320 321L_SAVE: 322 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 323 324 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 325 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 326 327 save_and_clear_ib_sts(s_save_tmp) 328 329 /* inform SPI the readiness and wait for SPI's go signal */ 330 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 331 s_mov_b32 s_save_exec_hi, exec_hi 332 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 333 334 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 335 336 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 337 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 338 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 339 340 L_SLEEP: 341 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 342 343 s_cbranch_execz L_SLEEP 344 345 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 346 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 347 get_vgpr_size_bytes(s_save_ttmps_lo) 348 get_sgpr_size_bytes(s_save_ttmps_hi) 349 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 350 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 351 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 352 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 353 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 354 ack_sqc_store_workaround() 355 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 356 ack_sqc_store_workaround() 357 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 358 ack_sqc_store_workaround() 359 360 /* setup Resource Contants */ 361 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 362 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 363 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 364 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 365 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 366 367 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 368 s_mov_b32 s_save_m0, m0 //save M0 369 370 /* global mem offset */ 371 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 372 373 374 375 376 /* save HW registers */ 377 ////////////////////////////// 378 379 L_SAVE_HWREG: 380 // HWREG SR memory offset : size(VGPR)+size(SGPR) 381 get_vgpr_size_bytes(s_save_mem_offset) 382 get_sgpr_size_bytes(s_save_tmp) 383 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 384 385 386 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 387 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 388 389 390 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 391 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 392 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 393 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 394 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 395 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 396 397 //s_save_trapsts conflicts with s_save_alloc_size 398 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 399 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 400 401 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 402 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 403 404 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 405 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 406 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 407 408 409 410 /* the first wave in the threadgroup */ 411 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 412 s_mov_b32 s_save_exec_hi, 0x0 413 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 414 415 416 /* save SGPRs */ 417 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 418 ////////////////////////////// 419 420 // SGPR SR memory offset : size(VGPR) 421 get_vgpr_size_bytes(s_save_mem_offset) 422 // TODO, change RSRC word to rearrange memory layout for SGPRS 423 424 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 425 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 426 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 427 428 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 429 430 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 431 432 433 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 434 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 435 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 436 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 437 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 438 439 s_mov_b32 m0, 0x0 //SGPR initial index value =0 440 s_nop 0x0 //Manually inserted wait states 441 L_SAVE_SGPR_LOOP: 442 // SGPR is allocated in 16 SGPR granularity 443 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 444 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 445 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 446 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 447 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 448 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 449 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 450 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 451 452 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 453 s_add_u32 m0, m0, 16 //next sgpr index 454 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 455 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 456 // restore s_save_buf_rsrc0,1 457 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 458 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 459 460 461 462 463 /* save first 4 VGPR, then LDS save could use */ 464 // each wave will alloc 4 vgprs at least... 465 ///////////////////////////////////////////////////////////////////////////////////// 466 467 s_mov_b32 s_save_mem_offset, 0 468 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 469 s_mov_b32 exec_hi, 0xFFFFFFFF 470 s_mov_b32 xnack_mask_lo, 0x0 471 s_mov_b32 xnack_mask_hi, 0x0 472 473 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 474 475 476 // VGPR Allocated in 4-GPR granularity 477 478if SAVE_AFTER_XNACK_ERROR 479 check_if_tcp_store_ok() 480 s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP 481 482 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 483 s_branch L_SAVE_LDS 484 485L_SAVE_FIRST_VGPRS_WITH_TCP: 486end 487 488 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 489 490 /* save LDS */ 491 ////////////////////////////// 492 493 L_SAVE_LDS: 494 495 // Change EXEC to all threads... 496 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 497 s_mov_b32 exec_hi, 0xFFFFFFFF 498 499 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 500 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 501 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 502 503 s_barrier //LDS is used? wait for other waves in the same TG 504 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 505 s_cbranch_scc0 L_SAVE_LDS_DONE 506 507 // first wave do LDS save; 508 509 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 510 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 511 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 512 513 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 514 // 515 get_vgpr_size_bytes(s_save_mem_offset) 516 get_sgpr_size_bytes(s_save_tmp) 517 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 518 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 519 520 521 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 522 523 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 524 525 526 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 527 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 528 529if SAVE_AFTER_XNACK_ERROR 530 check_if_tcp_store_ok() 531 s_cbranch_scc1 L_SAVE_LDS_WITH_TCP 532 533 v_lshlrev_b32 v2, 2, v3 534L_SAVE_LDS_LOOP_SQC: 535 ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40 536 s_waitcnt lgkmcnt(0) 537 538 write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset) 539 540 v_add_u32 v2, 0x200, v2 541 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 542 s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC 543 544 s_branch L_SAVE_LDS_DONE 545 546L_SAVE_LDS_WITH_TCP: 547end 548 549 v_mul_i32_i24 v2, v3, 8 // tid*8 550 v_mov_b32 v3, 256*2 551 s_mov_b32 m0, 0x10000 552 s_mov_b32 s0, s_save_buf_rsrc3 553 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 554 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 555 556L_SAVE_LDS_LOOP_VECTOR: 557 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 558 s_waitcnt lgkmcnt(0) 559 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 560// s_waitcnt vmcnt(0) 561// v_add_u32 v2, vcc[0:1], v2, v3 562 v_add_u32 v2, v2, v3 563 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 564 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 565 566 // restore rsrc3 567 s_mov_b32 s_save_buf_rsrc3, s0 568 569L_SAVE_LDS_DONE: 570 571 572 /* save VGPRs - set the Rest VGPRs */ 573 ////////////////////////////////////////////////////////////////////////////////////// 574 L_SAVE_VGPR: 575 // VGPR SR memory offset: 0 576 // TODO rearrange the RSRC words to use swizzle for VGPR save... 577 578 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 579 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 580 s_mov_b32 exec_hi, 0xFFFFFFFF 581 582 get_num_arch_vgprs(s_save_alloc_size) 583 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 584 585 586 // VGPR store using dw burst 587 s_mov_b32 m0, 0x4 //VGPR initial index value =0 588 s_cmp_lt_u32 m0, s_save_alloc_size 589 s_cbranch_scc0 L_SAVE_VGPR_END 590 591 592 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 593 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 594 595if SAVE_AFTER_XNACK_ERROR 596 check_if_tcp_store_ok() 597 s_cbranch_scc1 L_SAVE_VGPR_LOOP 598 599L_SAVE_VGPR_LOOP_SQC: 600 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 601 602 s_add_u32 m0, m0, 4 603 s_cmp_lt_u32 m0, s_save_alloc_size 604 s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC 605 606 s_set_gpr_idx_off 607 s_branch L_SAVE_VGPR_END 608end 609 610 L_SAVE_VGPR_LOOP: 611 v_mov_b32 v0, v0 //v0 = v[0+m0] 612 v_mov_b32 v1, v1 //v0 = v[0+m0] 613 v_mov_b32 v2, v2 //v0 = v[0+m0] 614 v_mov_b32 v3, v3 //v0 = v[0+m0] 615 616 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 617 618 s_add_u32 m0, m0, 4 //next vgpr index 619 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 620 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 621 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 622 s_set_gpr_idx_off 623 624L_SAVE_VGPR_END: 625 626#if ASIC_FAMILY >= CHIP_ARCTURUS 627 // Save ACC VGPRs 628 629#if ASIC_FAMILY >= CHIP_ALDEBARAN 630 // ACC VGPR count may differ from ARCH VGPR count. 631 get_num_acc_vgprs(s_save_alloc_size, s_save_tmp) 632 s_and_b32 s_save_alloc_size, s_save_alloc_size, s_save_alloc_size 633 s_cbranch_scc0 L_SAVE_ACCVGPR_END 634 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 635#endif 636 637 s_mov_b32 m0, 0x0 //VGPR initial index value =0 638 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 639 640if SAVE_AFTER_XNACK_ERROR 641 check_if_tcp_store_ok() 642 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 643 644L_SAVE_ACCVGPR_LOOP_SQC: 645 for var vgpr = 0; vgpr < 4; ++ vgpr 646 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 647 end 648 649 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 650 651 s_add_u32 m0, m0, 4 652 s_cmp_lt_u32 m0, s_save_alloc_size 653 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC 654 655 s_set_gpr_idx_off 656 s_branch L_SAVE_ACCVGPR_END 657end 658 659L_SAVE_ACCVGPR_LOOP: 660 for var vgpr = 0; vgpr < 4; ++ vgpr 661 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 662 end 663 664 write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset) 665 666 s_add_u32 m0, m0, 4 667 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 668 s_cmp_lt_u32 m0, s_save_alloc_size 669 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 670 s_set_gpr_idx_off 671 672L_SAVE_ACCVGPR_END: 673#endif 674 675 s_branch L_END_PGM 676 677 678 679/**************************************************************************/ 680/* restore routine */ 681/**************************************************************************/ 682 683L_RESTORE: 684 /* Setup Resource Contants */ 685 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 686 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 687 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 688 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 689 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 690 691 /* global mem offset */ 692// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 693 694 /* the first wave in the threadgroup */ 695 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 696 s_cbranch_scc0 L_RESTORE_VGPR 697 698 /* restore LDS */ 699 ////////////////////////////// 700 L_RESTORE_LDS: 701 702 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 703 s_mov_b32 exec_hi, 0xFFFFFFFF 704 705 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 706 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 707 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 708 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 709 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 710 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 711 712 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 713 // 714 get_vgpr_size_bytes(s_restore_mem_offset) 715 get_sgpr_size_bytes(s_restore_tmp) 716 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 717 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 718 719 720 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 721 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 722 723 L_RESTORE_LDS_LOOP: 724 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 725 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 726 s_add_u32 m0, m0, 256*2 // 128 DW 727 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 728 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 729 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 730 731 732 /* restore VGPRs */ 733 ////////////////////////////// 734 L_RESTORE_VGPR: 735 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 736 s_mov_b32 exec_hi, 0xFFFFFFFF 737 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 738 739 // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3. 740 get_num_arch_vgprs(s_restore_alloc_size) 741 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 742 743 // ARCH VGPRs at offset: 0 744 s_mov_b32 s_restore_mem_offset, 0x0 745 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 746 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 747 s_mov_b32 m0, 4 //VGPR initial index value = 1 748 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 749 750 L_RESTORE_VGPR_LOOP: 751 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 752 v_mov_b32 v0, v0 //v[0+m0] = v0 753 v_mov_b32 v1, v1 754 v_mov_b32 v2, v2 755 v_mov_b32 v3, v3 756 s_add_u32 m0, m0, 4 //next vgpr index 757 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 758 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 759 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 760 761#if ASIC_FAMILY >= CHIP_ALDEBARAN 762 // ACC VGPR count may differ from ARCH VGPR count. 763 get_num_acc_vgprs(s_restore_alloc_size, s_restore_tmp2) 764 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, s_restore_alloc_size 765 s_cbranch_scc0 L_RESTORE_ACCVGPR_END 766 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 767#endif 768 769#if ASIC_FAMILY >= CHIP_ARCTURUS 770 // ACC VGPRs at offset: size(ARCH VGPRs) 771 s_mov_b32 m0, 0 772 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 773 774 L_RESTORE_ACCVGPR_LOOP: 775 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset) 776 777 for var vgpr = 0; vgpr < 4; ++ vgpr 778 v_accvgpr_write acc[vgpr], v[vgpr] 779 end 780 781 s_add_u32 m0, m0, 4 //next vgpr index 782 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 783 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 784 s_cbranch_scc1 L_RESTORE_ACCVGPR_LOOP //VGPR restore (except v0) is complete? 785 L_RESTORE_ACCVGPR_END: 786#endif 787 788 s_set_gpr_idx_off 789 790 // Restore VGPRs 0-3 last, no longer needed. 791 read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset_save) 792 793 /* restore SGPRs */ 794 ////////////////////////////// 795 796 // SGPR SR memory offset : size(VGPR) 797 get_vgpr_size_bytes(s_restore_mem_offset) 798 get_sgpr_size_bytes(s_restore_tmp) 799 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 800 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 801 // TODO, change RSRC word to rearrange memory layout for SGPRS 802 803 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 804 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 805 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 806 807 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 808 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 809 810 s_mov_b32 m0, s_restore_alloc_size 811 812 L_RESTORE_SGPR_LOOP: 813 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 814 s_waitcnt lgkmcnt(0) //ensure data ready 815 816 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 817 s_nop 0 // hazard SALU M0=> S_MOVREL 818 819 s_movreld_b64 s0, s0 //s[0+m0] = s0 820 s_movreld_b64 s2, s2 821 s_movreld_b64 s4, s4 822 s_movreld_b64 s6, s6 823 s_movreld_b64 s8, s8 824 s_movreld_b64 s10, s10 825 s_movreld_b64 s12, s12 826 s_movreld_b64 s14, s14 827 828 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 829 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 830 831 /* restore HW registers */ 832 ////////////////////////////// 833 L_RESTORE_HWREG: 834 835 836 // HWREG SR memory offset : size(VGPR)+size(SGPR) 837 get_vgpr_size_bytes(s_restore_mem_offset) 838 get_sgpr_size_bytes(s_restore_tmp) 839 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 840 841 842 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 843 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 844 845 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 846 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 847 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 848 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 849 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 850 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 851 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 852 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 853 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 854 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 855 856 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 857 858 s_mov_b32 m0, s_restore_m0 859 s_mov_b32 exec_lo, s_restore_exec_lo 860 s_mov_b32 exec_hi, s_restore_exec_hi 861 862 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 863 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 864 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 865 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 866 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 867 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 868 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 869 870 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 871 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 872 get_vgpr_size_bytes(s_restore_ttmps_lo) 873 get_sgpr_size_bytes(s_restore_ttmps_hi) 874 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 875 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 876 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 877 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 878 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 879 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 880 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 881 s_waitcnt lgkmcnt(0) 882 883 restore_ib_sts(s_restore_tmp) 884 885 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 886 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 887 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 888 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 889 890 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 891 892 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 893 894 895/**************************************************************************/ 896/* the END */ 897/**************************************************************************/ 898L_END_PGM: 899 s_endpgm 900 901end 902 903 904/**************************************************************************/ 905/* the helper functions */ 906/**************************************************************************/ 907 908//Only for save hwreg to mem 909function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 910 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 911 s_mov_b32 m0, s_mem_offset 912 s_buffer_store_dword s, s_rsrc, m0 glc:1 913 ack_sqc_store_workaround() 914 s_add_u32 s_mem_offset, s_mem_offset, 4 915 s_mov_b32 m0, exec_lo 916end 917 918 919// HWREG are saved before SGPRs, so all HWREG could be use. 920function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 921 922 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 923 ack_sqc_store_workaround() 924 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 925 ack_sqc_store_workaround() 926 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 927 ack_sqc_store_workaround() 928 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 929 ack_sqc_store_workaround() 930 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 931 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 932end 933 934 935function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 936 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 937 s_add_u32 s_mem_offset, s_mem_offset, 4 938end 939 940function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 941 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 942 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 943end 944 945function check_if_tcp_store_ok 946 // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail. 947 s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK 948 s_cbranch_scc1 L_TCP_STORE_CHECK_DONE 949 950 s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) 951 s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp 952 953L_TCP_STORE_CHECK_DONE: 954end 955 956function write_4vgprs_to_mem(s_rsrc, s_mem_offset) 957 buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 958 buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 959 buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 960 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 961end 962 963function read_4vgprs_from_mem(s_rsrc, s_mem_offset) 964 buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 965 buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 966 buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 967 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 968 s_waitcnt vmcnt(0) 969end 970 971function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset) 972 s_mov_b32 s4, 0 973 974L_WRITE_VGPR_LANE_LOOP: 975 for var lane = 0; lane < 4; ++ lane 976 v_readlane_b32 s[lane], v, s4 977 s_add_u32 s4, s4, 1 978 end 979 980 s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1 981 ack_sqc_store_workaround() 982 983 s_add_u32 s_mem_offset, s_mem_offset, 0x10 984 s_cmp_eq_u32 s4, 0x40 985 s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP 986end 987 988function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset) 989 for var vgpr = 0; vgpr < n_vgprs; ++ vgpr 990 write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset) 991 end 992end 993 994function get_lds_size_bytes(s_lds_size_byte) 995 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 996 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 997 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 998end 999 1000function get_vgpr_size_bytes(s_vgpr_size_byte) 1001 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1002 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1003 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1004 1005#if ASIC_FAMILY >= CHIP_ARCTURUS 1006 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs 1007#endif 1008end 1009 1010function get_sgpr_size_bytes(s_sgpr_size_byte) 1011 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1012 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1013 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1014end 1015 1016function get_hwreg_size_bytes 1017 return 128 //HWREG size 128 bytes 1018end 1019 1020function get_num_arch_vgprs(s_num_arch_vgprs) 1021#if ASIC_FAMILY >= CHIP_ALDEBARAN 1022 // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count. 1023 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE) 1024#else 1025 s_getreg_b32 s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1026#endif 1027 1028 // Number of VGPRs = (vgpr_size + 1) * 4 1029 s_add_u32 s_num_arch_vgprs, s_num_arch_vgprs, 1 1030 s_lshl_b32 s_num_arch_vgprs, s_num_arch_vgprs, 2 1031end 1032 1033#if ASIC_FAMILY >= CHIP_ALDEBARAN 1034function get_num_acc_vgprs(s_num_acc_vgprs, s_tmp) 1035 // VGPR count = (GPR_ALLOC.VGPR_SIZE + 1) * 8 1036 s_getreg_b32 s_num_acc_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1037 s_add_u32 s_num_acc_vgprs, s_num_acc_vgprs, 1 1038 s_lshl_b32 s_num_acc_vgprs, s_num_acc_vgprs, 3 1039 1040 // ACC VGPR count = VGPR count - ARCH VGPR count. 1041 get_num_arch_vgprs(s_tmp) 1042 s_sub_u32 s_num_acc_vgprs, s_num_acc_vgprs, s_tmp 1043end 1044#endif 1045 1046function ack_sqc_store_workaround 1047 if ACK_SQC_STORE 1048 s_waitcnt lgkmcnt(0) 1049 end 1050end 1051 1052function set_status_without_spi_prio(status, tmp) 1053 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1054 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1055 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1056 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1057 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1058end 1059 1060function save_and_clear_ib_sts(tmp) 1061 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 1062 s_getreg_b32 tmp, hwreg(HW_REG_IB_STS) 1063 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1064 s_lshl_b32 tmp, tmp, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1065 s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 1066 s_or_b32 ttmp11, ttmp11, tmp 1067 s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0x0 1068end 1069 1070function restore_ib_sts(tmp) 1071 s_lshr_b32 tmp, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1072 s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1073 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp 1074end