kfd_int_process_v9.c (15032B)
1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#include "kfd_priv.h" 25#include "kfd_events.h" 26#include "soc15_int.h" 27#include "kfd_device_queue_manager.h" 28#include "kfd_smi_events.h" 29 30enum SQ_INTERRUPT_WORD_ENCODING { 31 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 32 SQ_INTERRUPT_WORD_ENCODING_INST, 33 SQ_INTERRUPT_WORD_ENCODING_ERROR, 34}; 35 36enum SQ_INTERRUPT_ERROR_TYPE { 37 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 38 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 39 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 40 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 41}; 42 43/* SQ_INTERRUPT_WORD_AUTO_CTXID */ 44#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 45#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 46#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 47#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 48#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 49#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 50#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 51#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 52#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 53#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 54#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 55 56#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 57#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 58#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 59#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 60#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 61#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 62#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 63#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 64#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 65#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 66#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 67 68/* SQ_INTERRUPT_WORD_WAVE_CTXID */ 69#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 70#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 71#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 72#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 73#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 74#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 75#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 76#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 77 78#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 79#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 80#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 81#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 82#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 83#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 84#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 85#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 86 87#define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 88 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 89 90#define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 91#define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 92 93static void event_interrupt_poison_consumption_v9(struct kfd_dev *dev, 94 uint16_t pasid, uint16_t client_id) 95{ 96 int old_poison, ret = -EINVAL; 97 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 98 99 if (!p) 100 return; 101 102 /* all queues of a process will be unmapped in one time */ 103 old_poison = atomic_cmpxchg(&p->poison, 0, 1); 104 kfd_unref_process(p); 105 if (old_poison) 106 return; 107 108 switch (client_id) { 109 case SOC15_IH_CLIENTID_SE0SH: 110 case SOC15_IH_CLIENTID_SE1SH: 111 case SOC15_IH_CLIENTID_SE2SH: 112 case SOC15_IH_CLIENTID_SE3SH: 113 case SOC15_IH_CLIENTID_UTCL2: 114 ret = kfd_dqm_evict_pasid(dev->dqm, pasid); 115 break; 116 case SOC15_IH_CLIENTID_SDMA0: 117 case SOC15_IH_CLIENTID_SDMA1: 118 case SOC15_IH_CLIENTID_SDMA2: 119 case SOC15_IH_CLIENTID_SDMA3: 120 case SOC15_IH_CLIENTID_SDMA4: 121 break; 122 default: 123 break; 124 } 125 126 kfd_signal_poison_consumed_event(dev, pasid); 127 128 /* resetting queue passes, do page retirement without gpu reset 129 * resetting queue fails, fallback to gpu reset solution 130 */ 131 if (!ret) { 132 dev_warn(dev->adev->dev, 133 "RAS poison consumption, unmap queue flow succeeded: client id %d\n", 134 client_id); 135 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); 136 } else { 137 dev_warn(dev->adev->dev, 138 "RAS poison consumption, fall back to gpu reset flow: client id %d\n", 139 client_id); 140 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); 141 } 142} 143 144static bool context_id_expected(struct kfd_dev *dev) 145{ 146 switch (KFD_GC_VERSION(dev)) { 147 case IP_VERSION(9, 0, 1): 148 return dev->mec_fw_version >= 0x817a; 149 case IP_VERSION(9, 1, 0): 150 case IP_VERSION(9, 2, 1): 151 case IP_VERSION(9, 2, 2): 152 case IP_VERSION(9, 3, 0): 153 case IP_VERSION(9, 4, 0): 154 return dev->mec_fw_version >= 0x17a; 155 default: 156 /* Other GFXv9 and later GPUs always sent valid context IDs 157 * on legitimate events 158 */ 159 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 1); 160 } 161} 162 163static bool event_interrupt_isr_v9(struct kfd_dev *dev, 164 const uint32_t *ih_ring_entry, 165 uint32_t *patched_ihre, 166 bool *patched_flag) 167{ 168 uint16_t source_id, client_id, pasid, vmid; 169 const uint32_t *data = ih_ring_entry; 170 171 /* Only handle interrupts from KFD VMIDs */ 172 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 173 if (vmid < dev->vm_info.first_vmid_kfd || 174 vmid > dev->vm_info.last_vmid_kfd) 175 return false; 176 177 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 178 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 179 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 180 181 /* Only handle clients we care about */ 182 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 183 client_id != SOC15_IH_CLIENTID_SDMA0 && 184 client_id != SOC15_IH_CLIENTID_SDMA1 && 185 client_id != SOC15_IH_CLIENTID_SDMA2 && 186 client_id != SOC15_IH_CLIENTID_SDMA3 && 187 client_id != SOC15_IH_CLIENTID_SDMA4 && 188 client_id != SOC15_IH_CLIENTID_SDMA5 && 189 client_id != SOC15_IH_CLIENTID_SDMA6 && 190 client_id != SOC15_IH_CLIENTID_SDMA7 && 191 client_id != SOC15_IH_CLIENTID_VMC && 192 client_id != SOC15_IH_CLIENTID_VMC1 && 193 client_id != SOC15_IH_CLIENTID_UTCL2 && 194 client_id != SOC15_IH_CLIENTID_SE0SH && 195 client_id != SOC15_IH_CLIENTID_SE1SH && 196 client_id != SOC15_IH_CLIENTID_SE2SH && 197 client_id != SOC15_IH_CLIENTID_SE3SH) 198 return false; 199 200 /* This is a known issue for gfx9. Under non HWS, pasid is not set 201 * in the interrupt payload, so we need to find out the pasid on our 202 * own. 203 */ 204 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 205 const uint32_t pasid_mask = 0xffff; 206 207 *patched_flag = true; 208 memcpy(patched_ihre, ih_ring_entry, 209 dev->device_info.ih_ring_entry_size); 210 211 pasid = dev->dqm->vmid_pasid[vmid]; 212 213 /* Patch the pasid field */ 214 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 215 & ~pasid_mask) | pasid); 216 } 217 218 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 219 client_id, source_id, vmid, pasid); 220 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 221 data[0], data[1], data[2], data[3], 222 data[4], data[5], data[6], data[7]); 223 224 /* If there is no valid PASID, it's likely a bug */ 225 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 226 return false; 227 228 /* Workaround CP firmware sending bogus signals with 0 context_id. 229 * Those can be safely ignored on hardware and firmware versions that 230 * include a valid context_id on legitimate signals. This avoids the 231 * slow path in kfd_signal_event_interrupt that scans all event slots 232 * for signaled events. 233 */ 234 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) { 235 uint32_t context_id = 236 SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 237 238 if (context_id == 0 && context_id_expected(dev)) 239 return false; 240 } 241 242 /* Interrupt types we care about: various signals and faults. 243 * They will be forwarded to a work queue (see below). 244 */ 245 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 246 source_id == SOC15_INTSRC_SDMA_TRAP || 247 source_id == SOC15_INTSRC_SDMA_ECC || 248 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 249 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 250 ((client_id == SOC15_IH_CLIENTID_VMC || 251 client_id == SOC15_IH_CLIENTID_VMC1 || 252 client_id == SOC15_IH_CLIENTID_UTCL2) && 253 !amdgpu_no_queue_eviction_on_vm_fault); 254} 255 256static void event_interrupt_wq_v9(struct kfd_dev *dev, 257 const uint32_t *ih_ring_entry) 258{ 259 uint16_t source_id, client_id, pasid, vmid; 260 uint32_t context_id0, context_id1; 261 uint32_t sq_intr_err, sq_int_data, encoding; 262 263 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 264 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 265 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 266 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 267 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 268 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 269 270 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 271 client_id == SOC15_IH_CLIENTID_SE0SH || 272 client_id == SOC15_IH_CLIENTID_SE1SH || 273 client_id == SOC15_IH_CLIENTID_SE2SH || 274 client_id == SOC15_IH_CLIENTID_SE3SH) { 275 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 276 kfd_signal_event_interrupt(pasid, context_id0, 32); 277 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 278 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 279 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 280 switch (encoding) { 281 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 282 pr_debug( 283 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 284 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 285 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 286 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 287 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 288 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 289 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 290 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 291 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 292 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 293 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 294 break; 295 case SQ_INTERRUPT_WORD_ENCODING_INST: 296 pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 297 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 298 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 299 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 300 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 301 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 302 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 303 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 304 sq_int_data); 305 break; 306 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 307 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 308 pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 309 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 310 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 311 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 312 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 313 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 314 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 315 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 316 sq_intr_err); 317 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 318 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 319 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 320 return; 321 } 322 break; 323 default: 324 break; 325 } 326 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); 327 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 328 kfd_signal_hw_exception_event(pasid); 329 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 330 client_id == SOC15_IH_CLIENTID_SDMA1 || 331 client_id == SOC15_IH_CLIENTID_SDMA2 || 332 client_id == SOC15_IH_CLIENTID_SDMA3 || 333 client_id == SOC15_IH_CLIENTID_SDMA4 || 334 client_id == SOC15_IH_CLIENTID_SDMA5 || 335 client_id == SOC15_IH_CLIENTID_SDMA6 || 336 client_id == SOC15_IH_CLIENTID_SDMA7) { 337 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 338 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 339 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 340 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 341 return; 342 } 343 } else if (client_id == SOC15_IH_CLIENTID_VMC || 344 client_id == SOC15_IH_CLIENTID_VMC1 || 345 client_id == SOC15_IH_CLIENTID_UTCL2) { 346 struct kfd_vm_fault_info info = {0}; 347 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 348 349 if (client_id == SOC15_IH_CLIENTID_UTCL2 && 350 amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev)) { 351 event_interrupt_poison_consumption_v9(dev, pasid, client_id); 352 return; 353 } 354 355 info.vmid = vmid; 356 info.mc_id = client_id; 357 info.page_addr = ih_ring_entry[4] | 358 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 359 info.prot_valid = ring_id & 0x08; 360 info.prot_read = ring_id & 0x10; 361 info.prot_write = ring_id & 0x20; 362 363 kfd_smi_event_update_vmfault(dev, pasid); 364 kfd_dqm_evict_pasid(dev->dqm, pasid); 365 kfd_signal_vm_fault_event(dev, pasid, &info); 366 } 367} 368 369const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 370 .interrupt_isr = event_interrupt_isr_v9, 371 .interrupt_wq = event_interrupt_wq_v9, 372};