cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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kfd_mqd_manager.c (7940B)


      1// SPDX-License-Identifier: GPL-2.0 OR MIT
      2/*
      3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be included in
     13 * all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     21 * OTHER DEALINGS IN THE SOFTWARE.
     22 *
     23 */
     24
     25#include "kfd_mqd_manager.h"
     26#include "amdgpu_amdkfd.h"
     27#include "kfd_device_queue_manager.h"
     28
     29/* Mapping queue priority to pipe priority, indexed by queue priority */
     30int pipe_priority_map[] = {
     31	KFD_PIPE_PRIORITY_CS_LOW,
     32	KFD_PIPE_PRIORITY_CS_LOW,
     33	KFD_PIPE_PRIORITY_CS_LOW,
     34	KFD_PIPE_PRIORITY_CS_LOW,
     35	KFD_PIPE_PRIORITY_CS_LOW,
     36	KFD_PIPE_PRIORITY_CS_LOW,
     37	KFD_PIPE_PRIORITY_CS_LOW,
     38	KFD_PIPE_PRIORITY_CS_MEDIUM,
     39	KFD_PIPE_PRIORITY_CS_MEDIUM,
     40	KFD_PIPE_PRIORITY_CS_MEDIUM,
     41	KFD_PIPE_PRIORITY_CS_MEDIUM,
     42	KFD_PIPE_PRIORITY_CS_HIGH,
     43	KFD_PIPE_PRIORITY_CS_HIGH,
     44	KFD_PIPE_PRIORITY_CS_HIGH,
     45	KFD_PIPE_PRIORITY_CS_HIGH,
     46	KFD_PIPE_PRIORITY_CS_HIGH
     47};
     48
     49struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev, struct queue_properties *q)
     50{
     51	struct kfd_mem_obj *mqd_mem_obj = NULL;
     52
     53	mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
     54	if (!mqd_mem_obj)
     55		return NULL;
     56
     57	mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
     58	mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
     59	mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
     60
     61	return mqd_mem_obj;
     62}
     63
     64struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_dev *dev,
     65					struct queue_properties *q)
     66{
     67	struct kfd_mem_obj *mqd_mem_obj = NULL;
     68	uint64_t offset;
     69
     70	mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
     71	if (!mqd_mem_obj)
     72		return NULL;
     73
     74	offset = (q->sdma_engine_id *
     75		dev->device_info.num_sdma_queues_per_engine +
     76		q->sdma_queue_id) *
     77		dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
     78
     79	offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
     80
     81	mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
     82				+ offset);
     83	mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
     84	mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
     85				dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
     86
     87	return mqd_mem_obj;
     88}
     89
     90void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
     91			struct kfd_mem_obj *mqd_mem_obj)
     92{
     93	WARN_ON(!mqd_mem_obj->gtt_mem);
     94	kfree(mqd_mem_obj);
     95}
     96
     97void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
     98		const uint32_t *cu_mask, uint32_t cu_mask_count,
     99		uint32_t *se_mask)
    100{
    101	struct kfd_cu_info cu_info;
    102	uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
    103	int i, se, sh, cu, cu_bitmap_sh_mul;
    104
    105	amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
    106
    107	if (cu_mask_count > cu_info.cu_active_number)
    108		cu_mask_count = cu_info.cu_active_number;
    109
    110	/* Exceeding these bounds corrupts the stack and indicates a coding error.
    111	 * Returning with no CU's enabled will hang the queue, which should be
    112	 * attention grabbing.
    113	 */
    114	if (cu_info.num_shader_engines > KFD_MAX_NUM_SE) {
    115		pr_err("Exceeded KFD_MAX_NUM_SE, chip reports %d\n", cu_info.num_shader_engines);
    116		return;
    117	}
    118	if (cu_info.num_shader_arrays_per_engine > KFD_MAX_NUM_SH_PER_SE) {
    119		pr_err("Exceeded KFD_MAX_NUM_SH, chip reports %d\n",
    120			cu_info.num_shader_arrays_per_engine * cu_info.num_shader_engines);
    121		return;
    122	}
    123
    124	cu_bitmap_sh_mul = (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0) &&
    125			    KFD_GC_VERSION(mm->dev) < IP_VERSION(12, 0, 0)) ? 2 : 1;
    126
    127	/* Count active CUs per SH.
    128	 *
    129	 * Some CUs in an SH may be disabled.	HW expects disabled CUs to be
    130	 * represented in the high bits of each SH's enable mask (the upper and lower
    131	 * 16 bits of se_mask) and will take care of the actual distribution of
    132	 * disabled CUs within each SH automatically.
    133	 * Each half of se_mask must be filled only on bits 0-cu_per_sh[se][sh]-1.
    134	 *
    135	 * See note on Arcturus cu_bitmap layout in gfx_v9_0_get_cu_info.
    136	 * See note on GFX11 cu_bitmap layout in gfx_v11_0_get_cu_info.
    137	 */
    138	for (se = 0; se < cu_info.num_shader_engines; se++)
    139		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
    140			cu_per_sh[se][sh] = hweight32(
    141				cu_info.cu_bitmap[se % 4][sh + (se / 4) * cu_bitmap_sh_mul]);
    142
    143	/* Symmetrically map cu_mask to all SEs & SHs:
    144	 * se_mask programs up to 2 SH in the upper and lower 16 bits.
    145	 *
    146	 * Examples
    147	 * Assuming 1 SH/SE, 4 SEs:
    148	 * cu_mask[0] bit0 -> se_mask[0] bit0
    149	 * cu_mask[0] bit1 -> se_mask[1] bit0
    150	 * ...
    151	 * cu_mask[0] bit4 -> se_mask[0] bit1
    152	 * ...
    153	 *
    154	 * Assuming 2 SH/SE, 4 SEs
    155	 * cu_mask[0] bit0 -> se_mask[0] bit0 (SE0,SH0,CU0)
    156	 * cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0)
    157	 * ...
    158	 * cu_mask[0] bit4 -> se_mask[0] bit16 (SE0,SH1,CU0)
    159	 * cu_mask[0] bit5 -> se_mask[1] bit16 (SE1,SH1,CU0)
    160	 * ...
    161	 * cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1)
    162	 * ...
    163	 *
    164	 * First ensure all CUs are disabled, then enable user specified CUs.
    165	 */
    166	for (i = 0; i < cu_info.num_shader_engines; i++)
    167		se_mask[i] = 0;
    168
    169	i = 0;
    170	for (cu = 0; cu < 16; cu++) {
    171		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
    172			for (se = 0; se < cu_info.num_shader_engines; se++) {
    173				if (cu_per_sh[se][sh] > cu) {
    174					if (cu_mask[i / 32] & (1 << (i % 32)))
    175						se_mask[se] |= 1 << (cu + sh * 16);
    176					i++;
    177					if (i == cu_mask_count)
    178						return;
    179				}
    180			}
    181		}
    182	}
    183}
    184
    185int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
    186		     uint32_t pipe_id, uint32_t queue_id,
    187		     struct queue_properties *p, struct mm_struct *mms)
    188{
    189	return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id,
    190					      queue_id, p->doorbell_off);
    191}
    192
    193int kfd_destroy_mqd_cp(struct mqd_manager *mm, void *mqd,
    194		enum kfd_preempt_type type, unsigned int timeout,
    195		uint32_t pipe_id, uint32_t queue_id)
    196{
    197	return mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, mqd, type, timeout,
    198						pipe_id, queue_id);
    199}
    200
    201void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,
    202	      struct kfd_mem_obj *mqd_mem_obj)
    203{
    204	if (mqd_mem_obj->gtt_mem) {
    205		amdgpu_amdkfd_free_gtt_mem(mm->dev->adev, mqd_mem_obj->gtt_mem);
    206		kfree(mqd_mem_obj);
    207	} else {
    208		kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
    209	}
    210}
    211
    212bool kfd_is_occupied_cp(struct mqd_manager *mm, void *mqd,
    213		 uint64_t queue_address, uint32_t pipe_id,
    214		 uint32_t queue_id)
    215{
    216	return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->adev, queue_address,
    217						pipe_id, queue_id);
    218}
    219
    220int kfd_load_mqd_sdma(struct mqd_manager *mm, void *mqd,
    221		  uint32_t pipe_id, uint32_t queue_id,
    222		  struct queue_properties *p, struct mm_struct *mms)
    223{
    224	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd,
    225						(uint32_t __user *)p->write_ptr,
    226						mms);
    227}
    228
    229/*
    230 * preempt type here is ignored because there is only one way
    231 * to preempt sdma queue
    232 */
    233int kfd_destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
    234		     enum kfd_preempt_type type,
    235		     unsigned int timeout, uint32_t pipe_id,
    236		     uint32_t queue_id)
    237{
    238	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout);
    239}
    240
    241bool kfd_is_occupied_sdma(struct mqd_manager *mm, void *mqd,
    242		      uint64_t queue_address, uint32_t pipe_id,
    243		      uint32_t queue_id)
    244{
    245	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd);
    246}