cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

kfd_mqd_manager_v10.c (14616B)


      1// SPDX-License-Identifier: GPL-2.0 OR MIT
      2/*
      3 * Copyright 2018-2022 Advanced Micro Devices, Inc.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be included in
     13 * all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     21 * OTHER DEALINGS IN THE SOFTWARE.
     22 *
     23 */
     24
     25#include <linux/printk.h>
     26#include <linux/slab.h>
     27#include <linux/uaccess.h>
     28#include "kfd_priv.h"
     29#include "kfd_mqd_manager.h"
     30#include "v10_structs.h"
     31#include "gc/gc_10_1_0_offset.h"
     32#include "gc/gc_10_1_0_sh_mask.h"
     33#include "amdgpu_amdkfd.h"
     34
     35static inline struct v10_compute_mqd *get_mqd(void *mqd)
     36{
     37	return (struct v10_compute_mqd *)mqd;
     38}
     39
     40static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
     41{
     42	return (struct v10_sdma_mqd *)mqd;
     43}
     44
     45static void update_cu_mask(struct mqd_manager *mm, void *mqd,
     46			struct mqd_update_info *minfo)
     47{
     48	struct v10_compute_mqd *m;
     49	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
     50
     51	if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||
     52	    !minfo->cu_mask.ptr)
     53		return;
     54
     55	mqd_symmetrically_map_cu_mask(mm,
     56		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
     57
     58	m = get_mqd(mqd);
     59	m->compute_static_thread_mgmt_se0 = se_mask[0];
     60	m->compute_static_thread_mgmt_se1 = se_mask[1];
     61	m->compute_static_thread_mgmt_se2 = se_mask[2];
     62	m->compute_static_thread_mgmt_se3 = se_mask[3];
     63
     64	pr_debug("update cu mask to %#x %#x %#x %#x\n",
     65		m->compute_static_thread_mgmt_se0,
     66		m->compute_static_thread_mgmt_se1,
     67		m->compute_static_thread_mgmt_se2,
     68		m->compute_static_thread_mgmt_se3);
     69}
     70
     71static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
     72{
     73	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
     74	m->cp_hqd_queue_priority = q->priority;
     75}
     76
     77static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
     78		struct queue_properties *q)
     79{
     80	struct kfd_mem_obj *mqd_mem_obj;
     81
     82	if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
     83			&mqd_mem_obj))
     84		return NULL;
     85
     86	return mqd_mem_obj;
     87}
     88
     89static void init_mqd(struct mqd_manager *mm, void **mqd,
     90			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
     91			struct queue_properties *q)
     92{
     93	uint64_t addr;
     94	struct v10_compute_mqd *m;
     95
     96	m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
     97	addr = mqd_mem_obj->gpu_addr;
     98
     99	memset(m, 0, sizeof(struct v10_compute_mqd));
    100
    101	m->header = 0xC0310800;
    102	m->compute_pipelinestat_enable = 1;
    103	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
    104	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
    105	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
    106	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
    107
    108	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
    109			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
    110
    111	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
    112
    113	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
    114	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
    115
    116	m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
    117			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
    118			1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
    119
    120	if (q->format == KFD_QUEUE_FORMAT_AQL) {
    121		m->cp_hqd_aql_control =
    122			1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
    123	}
    124
    125	if (mm->dev->cwsr_enabled) {
    126		m->cp_hqd_persistent_state |=
    127			(1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
    128		m->cp_hqd_ctx_save_base_addr_lo =
    129			lower_32_bits(q->ctx_save_restore_area_address);
    130		m->cp_hqd_ctx_save_base_addr_hi =
    131			upper_32_bits(q->ctx_save_restore_area_address);
    132		m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
    133		m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
    134		m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
    135		m->cp_hqd_wg_state_offset = q->ctl_stack_size;
    136	}
    137
    138	*mqd = m;
    139	if (gart_addr)
    140		*gart_addr = addr;
    141	mm->update_mqd(mm, m, q, NULL);
    142}
    143
    144static int load_mqd(struct mqd_manager *mm, void *mqd,
    145			uint32_t pipe_id, uint32_t queue_id,
    146			struct queue_properties *p, struct mm_struct *mms)
    147{
    148	int r = 0;
    149	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
    150	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
    151
    152	r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
    153					  (uint32_t __user *)p->write_ptr,
    154					  wptr_shift, 0, mms);
    155	return r;
    156}
    157
    158static void update_mqd(struct mqd_manager *mm, void *mqd,
    159			struct queue_properties *q,
    160			struct mqd_update_info *minfo)
    161{
    162	struct v10_compute_mqd *m;
    163
    164	m = get_mqd(mqd);
    165
    166	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
    167	m->cp_hqd_pq_control |=
    168			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
    169	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
    170
    171	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
    172	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
    173
    174	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
    175	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
    176	m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
    177	m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
    178
    179	m->cp_hqd_pq_doorbell_control =
    180		q->doorbell_off <<
    181			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
    182	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
    183			m->cp_hqd_pq_doorbell_control);
    184
    185	m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
    186
    187	/*
    188	 * HW does not clamp this field correctly. Maximum EOP queue size
    189	 * is constrained by per-SE EOP done signal count, which is 8-bit.
    190	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
    191	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
    192	 * is safe, giving a maximum field value of 0xA.
    193	 */
    194	m->cp_hqd_eop_control = min(0xA,
    195		ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
    196	m->cp_hqd_eop_base_addr_lo =
    197			lower_32_bits(q->eop_ring_buffer_address >> 8);
    198	m->cp_hqd_eop_base_addr_hi =
    199			upper_32_bits(q->eop_ring_buffer_address >> 8);
    200
    201	m->cp_hqd_iq_timer = 0;
    202
    203	m->cp_hqd_vmid = q->vmid;
    204
    205	if (q->format == KFD_QUEUE_FORMAT_AQL) {
    206		/* GC 10 removed WPP_CLAMP from PQ Control */
    207		m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
    208				2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
    209				1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;
    210		m->cp_hqd_pq_doorbell_control |=
    211			1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
    212	}
    213	if (mm->dev->cwsr_enabled)
    214		m->cp_hqd_ctx_save_control = 0;
    215
    216	update_cu_mask(mm, mqd, minfo);
    217	set_priority(m, q);
    218
    219	q->is_active = QUEUE_IS_ACTIVE(*q);
    220}
    221
    222static uint32_t read_doorbell_id(void *mqd)
    223{
    224	struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd;
    225
    226	return m->queue_doorbell_id0;
    227}
    228
    229static int get_wave_state(struct mqd_manager *mm, void *mqd,
    230			  void __user *ctl_stack,
    231			  u32 *ctl_stack_used_size,
    232			  u32 *save_area_used_size)
    233{
    234	struct v10_compute_mqd *m;
    235
    236	m = get_mqd(mqd);
    237
    238	/* Control stack is written backwards, while workgroup context data
    239	 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
    240	 * Current position is at m->cp_hqd_cntl_stack_offset and
    241	 * m->cp_hqd_wg_state_offset, respectively.
    242	 */
    243	*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
    244		m->cp_hqd_cntl_stack_offset;
    245	*save_area_used_size = m->cp_hqd_wg_state_offset -
    246		m->cp_hqd_cntl_stack_size;
    247
    248	/* Control stack is not copied to user mode for GFXv10 because
    249	 * it's part of the context save area that is already
    250	 * accessible to user mode
    251	 */
    252
    253	return 0;
    254}
    255
    256static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
    257{
    258	struct v10_compute_mqd *m;
    259
    260	m = get_mqd(mqd);
    261
    262	memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd));
    263}
    264
    265static void restore_mqd(struct mqd_manager *mm, void **mqd,
    266			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
    267			struct queue_properties *qp,
    268			const void *mqd_src,
    269			const void *ctl_stack_src, const u32 ctl_stack_size)
    270{
    271	uint64_t addr;
    272	struct v10_compute_mqd *m;
    273
    274	m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
    275	addr = mqd_mem_obj->gpu_addr;
    276
    277	memcpy(m, mqd_src, sizeof(*m));
    278
    279	*mqd = m;
    280	if (gart_addr)
    281		*gart_addr = addr;
    282
    283	m->cp_hqd_pq_doorbell_control =
    284		qp->doorbell_off <<
    285			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
    286	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
    287			m->cp_hqd_pq_doorbell_control);
    288
    289	qp->is_active = 0;
    290}
    291
    292static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
    293			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
    294			struct queue_properties *q)
    295{
    296	struct v10_compute_mqd *m;
    297
    298	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
    299
    300	m = get_mqd(*mqd);
    301
    302	m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
    303			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
    304}
    305
    306static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
    307		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
    308		struct queue_properties *q)
    309{
    310	struct v10_sdma_mqd *m;
    311
    312	m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
    313
    314	memset(m, 0, sizeof(struct v10_sdma_mqd));
    315
    316	*mqd = m;
    317	if (gart_addr)
    318		*gart_addr = mqd_mem_obj->gpu_addr;
    319
    320	mm->update_mqd(mm, m, q, NULL);
    321}
    322
    323#define SDMA_RLC_DUMMY_DEFAULT 0xf
    324
    325static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
    326			struct queue_properties *q,
    327			struct mqd_update_info *minfo)
    328{
    329	struct v10_sdma_mqd *m;
    330
    331	m = get_sdma_mqd(mqd);
    332	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
    333		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
    334		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
    335		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
    336		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
    337
    338	m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
    339	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
    340	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
    341	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
    342	m->sdmax_rlcx_doorbell_offset =
    343		q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
    344
    345	m->sdma_engine_id = q->sdma_engine_id;
    346	m->sdma_queue_id = q->sdma_queue_id;
    347	m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
    348
    349	q->is_active = QUEUE_IS_ACTIVE(*q);
    350}
    351
    352static void checkpoint_mqd_sdma(struct mqd_manager *mm,
    353				void *mqd,
    354				void *mqd_dst,
    355				void *ctl_stack_dst)
    356{
    357	struct v10_sdma_mqd *m;
    358
    359	m = get_sdma_mqd(mqd);
    360
    361	memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd));
    362}
    363
    364static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
    365			     struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
    366			     struct queue_properties *qp,
    367			     const void *mqd_src,
    368			     const void *ctl_stack_src,
    369			     const u32 ctl_stack_size)
    370{
    371	uint64_t addr;
    372	struct v10_sdma_mqd *m;
    373
    374	m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
    375	addr = mqd_mem_obj->gpu_addr;
    376
    377	memcpy(m, mqd_src, sizeof(*m));
    378
    379	m->sdmax_rlcx_doorbell_offset =
    380		qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
    381
    382	*mqd = m;
    383	if (gart_addr)
    384		*gart_addr = addr;
    385
    386	qp->is_active = 0;
    387}
    388
    389#if defined(CONFIG_DEBUG_FS)
    390
    391static int debugfs_show_mqd(struct seq_file *m, void *data)
    392{
    393	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
    394		     data, sizeof(struct v10_compute_mqd), false);
    395	return 0;
    396}
    397
    398static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
    399{
    400	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
    401		     data, sizeof(struct v10_sdma_mqd), false);
    402	return 0;
    403}
    404
    405#endif
    406
    407struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
    408		struct kfd_dev *dev)
    409{
    410	struct mqd_manager *mqd;
    411
    412	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
    413		return NULL;
    414
    415	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
    416	if (!mqd)
    417		return NULL;
    418
    419	mqd->dev = dev;
    420
    421	switch (type) {
    422	case KFD_MQD_TYPE_CP:
    423		pr_debug("%s@%i\n", __func__, __LINE__);
    424		mqd->allocate_mqd = allocate_mqd;
    425		mqd->init_mqd = init_mqd;
    426		mqd->free_mqd = kfd_free_mqd_cp;
    427		mqd->load_mqd = load_mqd;
    428		mqd->update_mqd = update_mqd;
    429		mqd->destroy_mqd = kfd_destroy_mqd_cp;
    430		mqd->is_occupied = kfd_is_occupied_cp;
    431		mqd->mqd_size = sizeof(struct v10_compute_mqd);
    432		mqd->get_wave_state = get_wave_state;
    433		mqd->checkpoint_mqd = checkpoint_mqd;
    434		mqd->restore_mqd = restore_mqd;
    435#if defined(CONFIG_DEBUG_FS)
    436		mqd->debugfs_show_mqd = debugfs_show_mqd;
    437#endif
    438		pr_debug("%s@%i\n", __func__, __LINE__);
    439		break;
    440	case KFD_MQD_TYPE_HIQ:
    441		pr_debug("%s@%i\n", __func__, __LINE__);
    442		mqd->allocate_mqd = allocate_hiq_mqd;
    443		mqd->init_mqd = init_mqd_hiq;
    444		mqd->free_mqd = free_mqd_hiq_sdma;
    445		mqd->load_mqd = kfd_hiq_load_mqd_kiq;
    446		mqd->update_mqd = update_mqd;
    447		mqd->destroy_mqd = kfd_destroy_mqd_cp;
    448		mqd->is_occupied = kfd_is_occupied_cp;
    449		mqd->mqd_size = sizeof(struct v10_compute_mqd);
    450#if defined(CONFIG_DEBUG_FS)
    451		mqd->debugfs_show_mqd = debugfs_show_mqd;
    452#endif
    453		mqd->read_doorbell_id = read_doorbell_id;
    454		pr_debug("%s@%i\n", __func__, __LINE__);
    455		break;
    456	case KFD_MQD_TYPE_DIQ:
    457		mqd->allocate_mqd = allocate_mqd;
    458		mqd->init_mqd = init_mqd_hiq;
    459		mqd->free_mqd = kfd_free_mqd_cp;
    460		mqd->load_mqd = load_mqd;
    461		mqd->update_mqd = update_mqd;
    462		mqd->destroy_mqd = kfd_destroy_mqd_cp;
    463		mqd->is_occupied = kfd_is_occupied_cp;
    464		mqd->mqd_size = sizeof(struct v10_compute_mqd);
    465#if defined(CONFIG_DEBUG_FS)
    466		mqd->debugfs_show_mqd = debugfs_show_mqd;
    467#endif
    468		break;
    469	case KFD_MQD_TYPE_SDMA:
    470		pr_debug("%s@%i\n", __func__, __LINE__);
    471		mqd->allocate_mqd = allocate_sdma_mqd;
    472		mqd->init_mqd = init_mqd_sdma;
    473		mqd->free_mqd = free_mqd_hiq_sdma;
    474		mqd->load_mqd = kfd_load_mqd_sdma;
    475		mqd->update_mqd = update_mqd_sdma;
    476		mqd->destroy_mqd = kfd_destroy_mqd_sdma;
    477		mqd->is_occupied = kfd_is_occupied_sdma;
    478		mqd->checkpoint_mqd = checkpoint_mqd_sdma;
    479		mqd->restore_mqd = restore_mqd_sdma;
    480		mqd->mqd_size = sizeof(struct v10_sdma_mqd);
    481#if defined(CONFIG_DEBUG_FS)
    482		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
    483#endif
    484		pr_debug("%s@%i\n", __func__, __LINE__);
    485		break;
    486	default:
    487		kfree(mqd);
    488		return NULL;
    489	}
    490
    491	return mqd;
    492}