cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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kfd_pm4_headers.h (3694B)


      1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
      2/*
      3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be included in
     13 * all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     21 * OTHER DEALINGS IN THE SOFTWARE.
     22 *
     23 */
     24
     25#ifndef KFD_PM4_HEADERS_H_
     26#define KFD_PM4_HEADERS_H_
     27
     28#ifndef PM4_MES_HEADER_DEFINED
     29#define PM4_MES_HEADER_DEFINED
     30union PM4_MES_TYPE_3_HEADER {
     31	struct {
     32		/* reserved */
     33		uint32_t reserved1:8;
     34		/* IT opcode */
     35		uint32_t opcode:8;
     36		/* number of DWORDs - 1 in the information body */
     37		uint32_t count:14;
     38		/* packet identifier. It should be 3 for type 3 packets */
     39		uint32_t type:2;
     40	};
     41	uint32_t u32all;
     42};
     43#endif /* PM4_MES_HEADER_DEFINED */
     44
     45
     46/*--------------------MES_MAP_PROCESS-------------------- */
     47
     48#ifndef PM4_MES_MAP_PROCESS_DEFINED
     49#define PM4_MES_MAP_PROCESS_DEFINED
     50
     51struct pm4_map_process {
     52	union {
     53		union PM4_MES_TYPE_3_HEADER header;	/* header */
     54		uint32_t ordinal1;
     55	};
     56
     57	union {
     58		struct {
     59			uint32_t pasid:16;
     60			uint32_t reserved1:8;
     61			uint32_t diq_enable:1;
     62			uint32_t process_quantum:7;
     63		} bitfields2;
     64		uint32_t ordinal2;
     65	};
     66
     67	union {
     68		struct {
     69			uint32_t page_table_base:28;
     70			uint32_t reserved3:4;
     71		} bitfields3;
     72		uint32_t ordinal3;
     73	};
     74
     75	uint32_t sh_mem_bases;
     76	uint32_t sh_mem_ape1_base;
     77	uint32_t sh_mem_ape1_limit;
     78	uint32_t sh_mem_config;
     79	uint32_t gds_addr_lo;
     80	uint32_t gds_addr_hi;
     81
     82	union {
     83		struct {
     84			uint32_t num_gws:6;
     85			uint32_t reserved4:2;
     86			uint32_t num_oac:4;
     87			uint32_t reserved5:4;
     88			uint32_t gds_size:6;
     89			uint32_t num_queues:10;
     90		} bitfields10;
     91		uint32_t ordinal10;
     92	};
     93
     94};
     95#endif
     96
     97#ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
     98#define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
     99
    100struct pm4_map_process_scratch_kv {
    101	union {
    102		union PM4_MES_TYPE_3_HEADER   header; /* header */
    103		uint32_t            ordinal1;
    104	};
    105
    106	union {
    107		struct {
    108			uint32_t pasid:16;
    109			uint32_t reserved1:8;
    110			uint32_t diq_enable:1;
    111			uint32_t process_quantum:7;
    112		} bitfields2;
    113		uint32_t ordinal2;
    114	};
    115
    116	union {
    117		struct {
    118			uint32_t page_table_base:28;
    119			uint32_t reserved2:4;
    120		} bitfields3;
    121		uint32_t ordinal3;
    122	};
    123
    124	uint32_t reserved3;
    125	uint32_t sh_mem_bases;
    126	uint32_t sh_mem_config;
    127	uint32_t sh_mem_ape1_base;
    128	uint32_t sh_mem_ape1_limit;
    129	uint32_t sh_hidden_private_base_vmid;
    130	uint32_t reserved4;
    131	uint32_t reserved5;
    132	uint32_t gds_addr_lo;
    133	uint32_t gds_addr_hi;
    134
    135	union {
    136		struct {
    137			uint32_t num_gws:6;
    138			uint32_t reserved6:2;
    139			uint32_t num_oac:4;
    140			uint32_t reserved7:4;
    141			uint32_t gds_size:6;
    142			uint32_t num_queues:10;
    143		} bitfields14;
    144		uint32_t ordinal14;
    145	};
    146
    147	uint32_t completion_signal_lo32;
    148uint32_t completion_signal_hi32;
    149};
    150#endif
    151
    152enum {
    153	CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
    154};
    155
    156#endif /* KFD_PM4_HEADERS_H_ */