cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_dm_psr.h (1677B)

      1/*
      2 * Copyright 2021 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#ifndef AMDGPU_DM_AMDGPU_DM_PSR_H_
     27#define AMDGPU_DM_AMDGPU_DM_PSR_H_
     28
     29#include "amdgpu.h"
     30
     31/* the number of pageflips before enabling psr */
     32#define AMDGPU_DM_PSR_ENTRY_DELAY 5
     33
     34void amdgpu_dm_set_psr_caps(struct dc_link *link);
     35bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
     36bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
     37bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
     38bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
     39
     40#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */