cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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command_table_helper2.c (7410B)

      1/*
      2 * Copyright 2012-15 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "dm_services.h"
     27
     28#include "ObjectID.h"
     29#include "atomfirmware.h"
     30
     31#include "include/bios_parser_types.h"
     32
     33#include "command_table_helper2.h"
     34
     35bool dal_bios_parser_init_cmd_tbl_helper2(
     36	const struct command_table_helper **h,
     37	enum dce_version dce)
     38{
     39	switch (dce) {
     40#if defined(CONFIG_DRM_AMD_DC_SI)
     41	case DCE_VERSION_6_0:
     42	case DCE_VERSION_6_1:
     43	case DCE_VERSION_6_4:
     44		*h = dal_cmd_tbl_helper_dce60_get_table();
     45		return true;
     46#endif
     47
     48	case DCE_VERSION_8_0:
     49	case DCE_VERSION_8_1:
     50	case DCE_VERSION_8_3:
     51		*h = dal_cmd_tbl_helper_dce80_get_table();
     52		return true;
     53
     54	case DCE_VERSION_10_0:
     55		*h = dal_cmd_tbl_helper_dce110_get_table();
     56		return true;
     57
     58	case DCE_VERSION_11_0:
     59		*h = dal_cmd_tbl_helper_dce110_get_table();
     60		return true;
     61
     62	case DCE_VERSION_11_2:
     63	case DCE_VERSION_11_22:
     64	case DCE_VERSION_12_0:
     65	case DCE_VERSION_12_1:
     66		*h = dal_cmd_tbl_helper_dce112_get_table2();
     67		return true;
     68	case DCN_VERSION_1_0:
     69	case DCN_VERSION_1_01:
     70	case DCN_VERSION_2_0:
     71	case DCN_VERSION_2_1:
     72	case DCN_VERSION_2_01:
     73	case DCN_VERSION_3_0:
     74	case DCN_VERSION_3_01:
     75	case DCN_VERSION_3_02:
     76	case DCN_VERSION_3_03:
     77	case DCN_VERSION_3_1:
     78	case DCN_VERSION_3_15:
     79	case DCN_VERSION_3_16:
     80		*h = dal_cmd_tbl_helper_dce112_get_table2();
     81		return true;
     82
     83	default:
     84		/* Unsupported DCE */
     85		BREAK_TO_DEBUGGER();
     86		return false;
     87	}
     88}
     89
     90/* real implementations */
     91
     92bool dal_cmd_table_helper_controller_id_to_atom2(
     93	enum controller_id id,
     94	uint8_t *atom_id)
     95{
     96	if (atom_id == NULL) {
     97		BREAK_TO_DEBUGGER();
     98		return false;
     99	}
    100
    101	switch (id) {
    102	case CONTROLLER_ID_D0:
    103		*atom_id = ATOM_CRTC1;
    104		return true;
    105	case CONTROLLER_ID_D1:
    106		*atom_id = ATOM_CRTC2;
    107		return true;
    108	case CONTROLLER_ID_D2:
    109		*atom_id = ATOM_CRTC3;
    110		return true;
    111	case CONTROLLER_ID_D3:
    112		*atom_id = ATOM_CRTC4;
    113		return true;
    114	case CONTROLLER_ID_D4:
    115		*atom_id = ATOM_CRTC5;
    116		return true;
    117	case CONTROLLER_ID_D5:
    118		*atom_id = ATOM_CRTC6;
    119		return true;
    120	/* TODO :case CONTROLLER_ID_UNDERLAY0:
    121		*atom_id = ATOM_UNDERLAY_PIPE0;
    122		return true;
    123	*/
    124	case CONTROLLER_ID_UNDEFINED:
    125		*atom_id = ATOM_CRTC_INVALID;
    126		return true;
    127	default:
    128		/* Wrong controller id */
    129		BREAK_TO_DEBUGGER();
    130		return false;
    131	}
    132}
    133
    134/**
    135 * dal_cmd_table_helper_transmitter_bp_to_atom2 - Translate the Transmitter to the
    136 *                                     corresponding ATOM BIOS value
    137 *  @t: transmitter
    138 *  returns: digitalTransmitter
    139 *    // =00: Digital Transmitter1 ( UNIPHY linkAB )
    140 *    // =01: Digital Transmitter2 ( UNIPHY linkCD )
    141 *    // =02: Digital Transmitter3 ( UNIPHY linkEF )
    142 */
    143uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
    144	enum transmitter t)
    145{
    146	switch (t) {
    147	case TRANSMITTER_UNIPHY_A:
    148	case TRANSMITTER_UNIPHY_B:
    149	case TRANSMITTER_TRAVIS_LCD:
    150		return 0;
    151	case TRANSMITTER_UNIPHY_C:
    152	case TRANSMITTER_UNIPHY_D:
    153		return 1;
    154	case TRANSMITTER_UNIPHY_E:
    155	case TRANSMITTER_UNIPHY_F:
    156		return 2;
    157	default:
    158		/* Invalid Transmitter Type! */
    159		BREAK_TO_DEBUGGER();
    160		return 0;
    161	}
    162}
    163
    164uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
    165	enum signal_type s,
    166	bool enable_dp_audio)
    167{
    168	switch (s) {
    169	case SIGNAL_TYPE_DVI_SINGLE_LINK:
    170	case SIGNAL_TYPE_DVI_DUAL_LINK:
    171		return ATOM_ENCODER_MODE_DVI;
    172	case SIGNAL_TYPE_HDMI_TYPE_A:
    173		return ATOM_ENCODER_MODE_HDMI;
    174	case SIGNAL_TYPE_LVDS:
    175		return ATOM_ENCODER_MODE_LVDS;
    176	case SIGNAL_TYPE_EDP:
    177	case SIGNAL_TYPE_DISPLAY_PORT_MST:
    178	case SIGNAL_TYPE_DISPLAY_PORT:
    179	case SIGNAL_TYPE_VIRTUAL:
    180		if (enable_dp_audio)
    181			return ATOM_ENCODER_MODE_DP_AUDIO;
    182		else
    183			return ATOM_ENCODER_MODE_DP;
    184	case SIGNAL_TYPE_RGB:
    185		return ATOM_ENCODER_MODE_CRT;
    186	default:
    187		return ATOM_ENCODER_MODE_CRT;
    188	}
    189}
    190
    191bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
    192	enum clock_source_id id,
    193	uint32_t *ref_clk_src_id)
    194{
    195	if (ref_clk_src_id == NULL) {
    196		BREAK_TO_DEBUGGER();
    197		return false;
    198	}
    199
    200	switch (id) {
    201	case CLOCK_SOURCE_ID_PLL1:
    202		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
    203		return true;
    204	case CLOCK_SOURCE_ID_PLL2:
    205		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
    206		return true;
    207	/*TODO:case CLOCK_SOURCE_ID_DCPLL:
    208		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
    209		return true;
    210	*/
    211	case CLOCK_SOURCE_ID_EXTERNAL:
    212		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
    213		return true;
    214	case CLOCK_SOURCE_ID_UNDEFINED:
    215		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
    216		return true;
    217	default:
    218		/* Unsupported clock source id */
    219		BREAK_TO_DEBUGGER();
    220		return false;
    221	}
    222}
    223
    224uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
    225	enum encoder_id id)
    226{
    227	switch (id) {
    228	case ENCODER_ID_INTERNAL_LVDS:
    229		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
    230	case ENCODER_ID_INTERNAL_TMDS1:
    231		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
    232	case ENCODER_ID_INTERNAL_TMDS2:
    233		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
    234	case ENCODER_ID_INTERNAL_DAC1:
    235		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
    236	case ENCODER_ID_INTERNAL_DAC2:
    237		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
    238	case ENCODER_ID_INTERNAL_LVTM1:
    239		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
    240	case ENCODER_ID_INTERNAL_HDMI:
    241		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
    242	case ENCODER_ID_EXTERNAL_TRAVIS:
    243		return ENCODER_OBJECT_ID_TRAVIS;
    244	case ENCODER_ID_EXTERNAL_NUTMEG:
    245		return ENCODER_OBJECT_ID_NUTMEG;
    246	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
    247		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
    248	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
    249		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
    250	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
    251		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
    252	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
    253		return ENCODER_OBJECT_ID_MVPU_FPGA;
    254	case ENCODER_ID_INTERNAL_DDI:
    255		return ENCODER_OBJECT_ID_INTERNAL_DDI;
    256	case ENCODER_ID_INTERNAL_UNIPHY:
    257		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
    258	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
    259		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
    260	case ENCODER_ID_INTERNAL_UNIPHY1:
    261		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
    262	case ENCODER_ID_INTERNAL_UNIPHY2:
    263		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
    264	case ENCODER_ID_INTERNAL_UNIPHY3:
    265		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
    266	case ENCODER_ID_INTERNAL_WIRELESS:
    267		return ENCODER_OBJECT_ID_INTERNAL_VCE;
    268	case ENCODER_ID_INTERNAL_VIRTUAL:
    269		return ENCODER_OBJECT_ID_NONE;
    270	case ENCODER_ID_UNKNOWN:
    271		return ENCODER_OBJECT_ID_NONE;
    272	default:
    273		/* Invalid encoder id */
    274		BREAK_TO_DEBUGGER();
    275		return ENCODER_OBJECT_ID_NONE;
    276	}
    277}