dcn301_smu.h (5171B)
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef DAL_DC_301_SMU_H_ 27#define DAL_DC_301_SMU_H_ 28 29#define SMU13_DRIVER_IF_VERSION 2 30 31typedef struct { 32 uint32_t fclk; 33 uint32_t memclk; 34 uint32_t voltage; 35} df_pstate_t; 36 37typedef struct { 38 uint32_t vclk; 39 uint32_t dclk; 40} vcn_clk_t; 41 42typedef enum { 43 DSPCLK_DCFCLK = 0, 44 DSPCLK_DISPCLK, 45 DSPCLK_PIXCLK, 46 DSPCLK_PHYCLK, 47 DSPCLK_COUNT, 48} DSPCLK_e; 49 50typedef struct { 51 uint16_t Freq; // in MHz 52 uint16_t Vid; // min voltage in SVI2 VID 53} DisplayClockTable_t; 54 55typedef struct { 56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 58 uint16_t MinMclk; 59 uint16_t MaxMclk; 60 61 uint8_t WmSetting; 62 uint8_t WmType; // Used for normal pstate change or memory retraining 63 uint8_t Padding[2]; 64} WatermarkRowGeneric_t; 65 66 67#define NUM_WM_RANGES 4 68 69typedef enum { 70 WM_SOCCLK = 0, 71 WM_DCFCLK, 72 WM_COUNT, 73} WM_CLOCK_e; 74 75typedef struct { 76 // Watermarks 77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 78 79 uint32_t MmHubPadding[7]; // SMU internal use 80} Watermarks_t; 81 82 83#define TABLE_WATERMARKS 1 84#define TABLE_DPMCLOCKS 4 // Called by Driver 85 86 87#define VG_NUM_DCFCLK_DPM_LEVELS 7 88#define VG_NUM_DISPCLK_DPM_LEVELS 7 89#define VG_NUM_DPPCLK_DPM_LEVELS 7 90#define VG_NUM_SOCCLK_DPM_LEVELS 7 91#define VG_NUM_ISPICLK_DPM_LEVELS 7 92#define VG_NUM_ISPXCLK_DPM_LEVELS 7 93#define VG_NUM_VCN_DPM_LEVELS 5 94#define VG_NUM_FCLK_DPM_LEVELS 4 95#define VG_NUM_SOC_VOLTAGE_LEVELS 8 96 97// copy from vgh/vangogh/pmfw_driver_if.h 98struct vg_dpm_clocks { 99 uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS]; 100 uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS]; 101 uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS]; 102 uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS]; 103 uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS]; 104 uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS]; 105 vcn_clk_t VcnClocks[VG_NUM_VCN_DPM_LEVELS]; 106 107 uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS]; 108 109 df_pstate_t DfPstateTable[VG_NUM_FCLK_DPM_LEVELS]; 110 111 uint32_t MinGfxClk; 112 uint32_t MaxGfxClk; 113 114 uint8_t NumDfPstatesEnabled; 115 uint8_t NumDcfclkLevelsEnabled; 116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk 117 uint8_t NumSocClkLevelsEnabled; 118 119 uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk 120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk 121 uint8_t spare[2]; 122}; 123 124struct smu_dpm_clks { 125 struct vg_dpm_clocks *dpm_clks; 126 union large_integer mc_address; 127}; 128 129struct watermarks { 130 // Watermarks 131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 132 133 uint32_t MmHubPadding[7]; // SMU internal use 134}; 135 136 137struct display_idle_optimization { 138 unsigned int df_request_disabled : 1; 139 unsigned int phy_ref_clk_off : 1; 140 unsigned int s0i2_rdy : 1; 141 unsigned int reserved : 29; 142}; 143 144union display_idle_optimization_u { 145 struct display_idle_optimization idle_info; 146 uint32_t data; 147}; 148 149 150int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 151int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 152int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 153int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 154int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); 155int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 156void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); 157void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 158void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 159void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 160void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 161void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 162void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 163 164#endif /* DAL_DC_301_SMU_H_ */