cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn315_smu.h (4901B)

      1/*
      2 * Copyright 2021 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#ifndef DAL_DC_315_SMU_H_
     27#define DAL_DC_315_SMU_H_
     28#include "os_types.h"
     29
     30#define PMFW_DRIVER_IF_VERSION 4
     31
     32#define NUM_DCFCLK_DPM_LEVELS   4
     33#define NUM_DISPCLK_DPM_LEVELS  4
     34#define NUM_DPPCLK_DPM_LEVELS   4
     35#define NUM_SOCCLK_DPM_LEVELS   4
     36#define NUM_VCN_DPM_LEVELS      4
     37#define NUM_SOC_VOLTAGE_LEVELS  4
     38#define NUM_DF_PSTATE_LEVELS    4
     39
     40
     41typedef struct {
     42  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
     43  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
     44  uint16_t MinMclk;
     45  uint16_t MaxMclk;
     46  uint8_t  WmSetting;
     47  uint8_t  WmType;  // Used for normal pstate change or memory retraining
     48  uint8_t  Padding[2];
     49} WatermarkRowGeneric_t;
     50
     51#define NUM_WM_RANGES 4
     52#define WM_PSTATE_CHG 0
     53#define WM_RETRAINING 1
     54
     55typedef enum {
     56  WM_SOCCLK = 0,
     57  WM_DCFCLK,
     58  WM_COUNT,
     59} WM_CLOCK_e;
     60
     61typedef struct {
     62  uint32_t FClk;
     63  uint32_t MemClk;
     64  uint32_t Voltage;
     65} DfPstateTable_t;
     66
     67//Freq in MHz
     68//Voltage in milli volts with 2 fractional bits
     69typedef struct {
     70  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
     71  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
     72  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
     73  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
     74  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
     75  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
     76  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
     77  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
     78  uint8_t  NumDcfClkLevelsEnabled;
     79  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
     80  uint8_t  NumSocClkLevelsEnabled;
     81  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
     82  uint8_t  NumDfPstatesEnabled;
     83  uint8_t  spare[3];
     84  uint32_t MinGfxClk;
     85  uint32_t MaxGfxClk;
     86} DpmClocks_315_t;
     87
     88struct dcn315_watermarks {
     89  // Watermarks
     90  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
     91  uint32_t MmHubPadding[7]; // SMU internal use
     92};
     93
     94struct dcn315_smu_dpm_clks {
     95	DpmClocks_315_t *dpm_clks;
     96	union large_integer mc_address;
     97};
     98
     99#define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
    100#define TABLE_DPMCLOCKS          4 // Called by Driver and VBIOS
    101
    102struct display_idle_optimization {
    103	unsigned int df_request_disabled : 1;
    104	unsigned int phy_ref_clk_off     : 1;
    105	unsigned int s0i2_rdy            : 1;
    106	unsigned int reserved            : 29;
    107};
    108
    109union display_idle_optimization_u {
    110	struct display_idle_optimization idle_info;
    111	uint32_t data;
    112};
    113
    114int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
    115int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
    116int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
    117int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
    118int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
    119void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
    120void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
    121void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
    122void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
    123void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
    124void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
    125void dcn315_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
    126void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
    127int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
    128int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
    129void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
    130#endif /* DAL_DC_315_SMU_H_ */