cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dmub_psr.c (13805B)


      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "dmub_psr.h"
     27#include "dc.h"
     28#include "dc_dmub_srv.h"
     29#include "dmub/dmub_srv.h"
     30#include "core_types.h"
     31
     32#define DC_TRACE_LEVEL_MESSAGE(...)	do {} while (0) /* do nothing */
     33
     34#define MAX_PIPES 6
     35
     36/*
     37 * Convert dmcub psr state to dmcu psr state.
     38 */
     39static enum dc_psr_state convert_psr_state(uint32_t raw_state)
     40{
     41	enum dc_psr_state state = PSR_STATE0;
     42
     43	if (raw_state == 0)
     44		state = PSR_STATE0;
     45	else if (raw_state == 0x10)
     46		state = PSR_STATE1;
     47	else if (raw_state == 0x11)
     48		state = PSR_STATE1a;
     49	else if (raw_state == 0x20)
     50		state = PSR_STATE2;
     51	else if (raw_state == 0x21)
     52		state = PSR_STATE2a;
     53	else if (raw_state == 0x22)
     54		state = PSR_STATE2b;
     55	else if (raw_state == 0x30)
     56		state = PSR_STATE3;
     57	else if (raw_state == 0x31)
     58		state = PSR_STATE3Init;
     59	else if (raw_state == 0x40)
     60		state = PSR_STATE4;
     61	else if (raw_state == 0x41)
     62		state = PSR_STATE4a;
     63	else if (raw_state == 0x42)
     64		state = PSR_STATE4b;
     65	else if (raw_state == 0x43)
     66		state = PSR_STATE4c;
     67	else if (raw_state == 0x44)
     68		state = PSR_STATE4d;
     69	else if (raw_state == 0x50)
     70		state = PSR_STATE5;
     71	else if (raw_state == 0x51)
     72		state = PSR_STATE5a;
     73	else if (raw_state == 0x52)
     74		state = PSR_STATE5b;
     75	else if (raw_state == 0x53)
     76		state = PSR_STATE5c;
     77
     78	return state;
     79}
     80
     81/*
     82 * Get PSR state from firmware.
     83 */
     84static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
     85{
     86	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
     87	uint32_t raw_state = 0;
     88	uint32_t retry_count = 0;
     89	enum dmub_status status;
     90
     91	do {
     92		// Send gpint command and wait for ack
     93		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
     94
     95		if (status == DMUB_STATUS_OK) {
     96			// GPINT was executed, get response
     97			dmub_srv_get_gpint_response(srv, &raw_state);
     98			*state = convert_psr_state(raw_state);
     99		} else
    100			// Return invalid state when GPINT times out
    101			*state = PSR_STATE_INVALID;
    102
    103	} while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
    104
    105	// Assert if max retry hit
    106	if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
    107		ASSERT(0);
    108		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
    109				WPP_BIT_FLAG_Firmware_PsrState,
    110				"Unable to get PSR state from FW.");
    111	} else
    112		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
    113				WPP_BIT_FLAG_Firmware_PsrState,
    114				"Got PSR state from FW. PSR state: %d, Retry count: %d",
    115				*state, retry_count);
    116}
    117
    118/*
    119 * Set PSR version.
    120 */
    121static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
    122{
    123	union dmub_rb_cmd cmd;
    124	struct dc_context *dc = dmub->ctx;
    125
    126	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
    127		return false;
    128
    129	memset(&cmd, 0, sizeof(cmd));
    130	cmd.psr_set_version.header.type = DMUB_CMD__PSR;
    131	cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
    132	switch (stream->link->psr_settings.psr_version) {
    133	case DC_PSR_VERSION_1:
    134		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
    135		break;
    136	case DC_PSR_VERSION_UNSUPPORTED:
    137	default:
    138		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
    139		break;
    140	}
    141
    142	if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED)
    143		return false;
    144
    145	cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
    146	cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
    147	cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
    148
    149	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    150	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    151	dc_dmub_srv_wait_idle(dc->dmub_srv);
    152
    153	return true;
    154}
    155
    156/*
    157 * Enable/Disable PSR.
    158 */
    159static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
    160{
    161	union dmub_rb_cmd cmd;
    162	struct dc_context *dc = dmub->ctx;
    163	uint32_t retry_count;
    164	enum dc_psr_state state = PSR_STATE0;
    165
    166	memset(&cmd, 0, sizeof(cmd));
    167	cmd.psr_enable.header.type = DMUB_CMD__PSR;
    168
    169	cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
    170	cmd.psr_enable.data.panel_inst = panel_inst;
    171
    172	if (enable)
    173		cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
    174	else
    175		cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
    176
    177	cmd.psr_enable.header.payload_bytes = 0; // Send header only
    178
    179	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    180	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    181	dc_dmub_srv_wait_idle(dc->dmub_srv);
    182
    183	/* Below loops 1000 x 500us = 500 ms.
    184	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
    185	 *  least a few frames. Should never hit the max retry assert below.
    186	 */
    187	if (wait) {
    188		for (retry_count = 0; retry_count <= 1000; retry_count++) {
    189			dmub_psr_get_state(dmub, &state, panel_inst);
    190
    191			if (enable) {
    192				if (state != PSR_STATE0)
    193					break;
    194			} else {
    195				if (state == PSR_STATE0)
    196					break;
    197			}
    198
    199			udelay(500);
    200		}
    201
    202		/* assert if max retry hit */
    203		if (retry_count >= 1000)
    204			ASSERT(0);
    205	}
    206}
    207
    208/*
    209 * Set PSR level.
    210 */
    211static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
    212{
    213	union dmub_rb_cmd cmd;
    214	enum dc_psr_state state = PSR_STATE0;
    215	struct dc_context *dc = dmub->ctx;
    216
    217	dmub_psr_get_state(dmub, &state, panel_inst);
    218
    219	if (state == PSR_STATE0)
    220		return;
    221
    222	memset(&cmd, 0, sizeof(cmd));
    223	cmd.psr_set_level.header.type = DMUB_CMD__PSR;
    224	cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
    225	cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
    226	cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
    227	cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
    228	cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
    229	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    230	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    231	dc_dmub_srv_wait_idle(dc->dmub_srv);
    232}
    233
    234/*
    235 * Set PSR power optimization flags.
    236 */
    237static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)
    238{
    239	union dmub_rb_cmd cmd;
    240	struct dc_context *dc = dmub->ctx;
    241
    242	memset(&cmd, 0, sizeof(cmd));
    243	cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR;
    244	cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT;
    245	cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data);
    246	cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
    247	cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;
    248	cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;
    249
    250	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    251	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    252	dc_dmub_srv_wait_idle(dc->dmub_srv);
    253}
    254
    255/*
    256 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
    257 */
    258static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
    259		struct dc_link *link,
    260		struct psr_context *psr_context,
    261		uint8_t panel_inst)
    262{
    263	union dmub_rb_cmd cmd;
    264	struct dc_context *dc = dmub->ctx;
    265	struct dmub_cmd_psr_copy_settings_data *copy_settings_data
    266		= &cmd.psr_copy_settings.psr_copy_settings_data;
    267	struct pipe_ctx *pipe_ctx = NULL;
    268	struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
    269	int i = 0;
    270
    271	for (i = 0; i < MAX_PIPES; i++) {
    272		if (res_ctx->pipe_ctx[i].stream &&
    273		    res_ctx->pipe_ctx[i].stream->link == link &&
    274		    res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
    275			pipe_ctx = &res_ctx->pipe_ctx[i];
    276			//TODO: refactor for multi edp support
    277			break;
    278		}
    279	}
    280
    281	if (!pipe_ctx)
    282		return false;
    283
    284	// First, set the psr version
    285	if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
    286		return false;
    287
    288	// Program DP DPHY fast training registers
    289	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
    290			psr_context->psrExitLinkTrainingRequired);
    291
    292	// Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
    293	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
    294			psr_context->sdpTransmitLineNumDeadline);
    295
    296	memset(&cmd, 0, sizeof(cmd));
    297	cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
    298	cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
    299	cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
    300
    301	// Hw insts
    302	copy_settings_data->dpphy_inst				= psr_context->transmitterId;
    303	copy_settings_data->aux_inst				= psr_context->channel;
    304	copy_settings_data->digfe_inst				= psr_context->engineId;
    305	copy_settings_data->digbe_inst				= psr_context->transmitterId;
    306
    307	copy_settings_data->mpcc_inst				= pipe_ctx->plane_res.mpcc_inst;
    308
    309	if (pipe_ctx->plane_res.dpp)
    310		copy_settings_data->dpp_inst			= pipe_ctx->plane_res.dpp->inst;
    311	else
    312		copy_settings_data->dpp_inst			= 0;
    313	if (pipe_ctx->stream_res.opp)
    314		copy_settings_data->opp_inst			= pipe_ctx->stream_res.opp->inst;
    315	else
    316		copy_settings_data->opp_inst			= 0;
    317	if (pipe_ctx->stream_res.tg)
    318		copy_settings_data->otg_inst			= pipe_ctx->stream_res.tg->inst;
    319	else
    320		copy_settings_data->otg_inst			= 0;
    321
    322	// Misc
    323	copy_settings_data->use_phy_fsm             = link->ctx->dc->debug.psr_power_use_phy_fsm;
    324	copy_settings_data->psr_level				= psr_context->psr_level.u32all;
    325	copy_settings_data->smu_optimizations_en		= psr_context->allow_smu_optimizations;
    326	copy_settings_data->multi_disp_optimizations_en	= psr_context->allow_multi_disp_optimizations;
    327	copy_settings_data->frame_delay				= psr_context->frame_delay;
    328	copy_settings_data->frame_cap_ind			= psr_context->psrFrameCaptureIndicationReq;
    329	copy_settings_data->init_sdp_deadline			= psr_context->sdpTransmitLineNumDeadline;
    330	copy_settings_data->debug.u32All = 0;
    331	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
    332	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
    333	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
    334	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
    335	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
    336	copy_settings_data->panel_inst = panel_inst;
    337	copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
    338
    339	if (link->fec_state == dc_link_fec_enabled &&
    340		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
    341			sizeof(link->dpcd_caps.sink_dev_id_str)) ||
    342		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
    343			sizeof(link->dpcd_caps.sink_dev_id_str))))
    344		copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1;
    345	else
    346		copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
    347
    348	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    349	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    350	dc_dmub_srv_wait_idle(dc->dmub_srv);
    351
    352	return true;
    353}
    354
    355/*
    356 * Send command to PSR to force static ENTER and ignore all state changes until exit
    357 */
    358static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
    359{
    360	union dmub_rb_cmd cmd;
    361	struct dc_context *dc = dmub->ctx;
    362
    363	memset(&cmd, 0, sizeof(cmd));
    364
    365	cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
    366	cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
    367	cmd.psr_force_static.header.type = DMUB_CMD__PSR;
    368	cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
    369	cmd.psr_enable.header.payload_bytes = 0;
    370
    371	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
    372	dc_dmub_srv_cmd_execute(dc->dmub_srv);
    373	dc_dmub_srv_wait_idle(dc->dmub_srv);
    374}
    375
    376/*
    377 * Get PSR residency from firmware.
    378 */
    379static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
    380{
    381	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
    382	uint16_t param = (uint16_t)(panel_inst << 8);
    383
    384	/* Send gpint command and wait for ack */
    385	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
    386
    387	dmub_srv_get_gpint_response(srv, residency);
    388}
    389
    390static const struct dmub_psr_funcs psr_funcs = {
    391	.psr_copy_settings		= dmub_psr_copy_settings,
    392	.psr_enable			= dmub_psr_enable,
    393	.psr_get_state			= dmub_psr_get_state,
    394	.psr_set_level			= dmub_psr_set_level,
    395	.psr_force_static		= dmub_psr_force_static,
    396	.psr_get_residency		= dmub_psr_get_residency,
    397	.psr_set_power_opt		= dmub_psr_set_power_opt,
    398};
    399
    400/*
    401 * Construct PSR object.
    402 */
    403static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
    404{
    405	psr->ctx = ctx;
    406	psr->funcs = &psr_funcs;
    407}
    408
    409/*
    410 * Allocate and initialize PSR object.
    411 */
    412struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
    413{
    414	struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
    415
    416	if (psr == NULL) {
    417		BREAK_TO_DEBUGGER();
    418		return NULL;
    419	}
    420
    421	dmub_psr_construct(psr, ctx);
    422
    423	return psr;
    424}
    425
    426/*
    427 * Deallocate PSR object.
    428 */
    429void dmub_psr_destroy(struct dmub_psr **dmub)
    430{
    431	kfree(*dmub);
    432	*dmub = NULL;
    433}