cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dce80_resource.c (39345B)


      1/*
      2 * Copyright 2012-15 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include <linux/slab.h>
     27
     28#include "dce/dce_8_0_d.h"
     29#include "dce/dce_8_0_sh_mask.h"
     30
     31#include "dm_services.h"
     32
     33#include "link_encoder.h"
     34#include "stream_encoder.h"
     35
     36#include "resource.h"
     37#include "include/irq_service_interface.h"
     38#include "irq/dce80/irq_service_dce80.h"
     39#include "dce110/dce110_timing_generator.h"
     40#include "dce110/dce110_resource.h"
     41#include "dce80/dce80_timing_generator.h"
     42#include "dce/dce_mem_input.h"
     43#include "dce/dce_link_encoder.h"
     44#include "dce/dce_stream_encoder.h"
     45#include "dce/dce_ipp.h"
     46#include "dce/dce_transform.h"
     47#include "dce/dce_opp.h"
     48#include "dce/dce_clock_source.h"
     49#include "dce/dce_audio.h"
     50#include "dce/dce_hwseq.h"
     51#include "dce80/dce80_hw_sequencer.h"
     52#include "dce100/dce100_resource.h"
     53#include "dce/dce_panel_cntl.h"
     54
     55#include "reg_helper.h"
     56
     57#include "dce/dce_dmcu.h"
     58#include "dce/dce_aux.h"
     59#include "dce/dce_abm.h"
     60#include "dce/dce_i2c.h"
     61/* TODO remove this include */
     62
     63#include "dce80_resource.h"
     64
     65#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
     66#include "gmc/gmc_7_1_d.h"
     67#include "gmc/gmc_7_1_sh_mask.h"
     68#endif
     69
     70#ifndef mmDP_DPHY_INTERNAL_CTRL
     71#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
     72#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
     73#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
     74#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
     75#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
     76#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
     77#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
     78#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
     79#endif
     80
     81
     82#ifndef mmBIOS_SCRATCH_2
     83	#define mmBIOS_SCRATCH_2 0x05CB
     84	#define mmBIOS_SCRATCH_3 0x05CC
     85	#define mmBIOS_SCRATCH_6 0x05CF
     86#endif
     87
     88#ifndef mmDP_DPHY_FAST_TRAINING
     89	#define mmDP_DPHY_FAST_TRAINING                         0x1CCE
     90	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
     91	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
     92	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
     93	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
     94	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
     95	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
     96	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
     97#endif
     98
     99
    100#ifndef mmHPD_DC_HPD_CONTROL
    101	#define mmHPD_DC_HPD_CONTROL                            0x189A
    102	#define mmHPD0_DC_HPD_CONTROL                           0x189A
    103	#define mmHPD1_DC_HPD_CONTROL                           0x18A2
    104	#define mmHPD2_DC_HPD_CONTROL                           0x18AA
    105	#define mmHPD3_DC_HPD_CONTROL                           0x18B2
    106	#define mmHPD4_DC_HPD_CONTROL                           0x18BA
    107	#define mmHPD5_DC_HPD_CONTROL                           0x18C2
    108#endif
    109
    110#define DCE11_DIG_FE_CNTL 0x4a00
    111#define DCE11_DIG_BE_CNTL 0x4a47
    112#define DCE11_DP_SEC 0x4ac3
    113
    114static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
    115		{
    116			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
    117			.dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
    118			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
    119					- mmDPG_WATERMARK_MASK_CONTROL),
    120		},
    121		{
    122			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
    123			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
    124			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
    125					- mmDPG_WATERMARK_MASK_CONTROL),
    126		},
    127		{
    128			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
    129			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
    130			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
    131					- mmDPG_WATERMARK_MASK_CONTROL),
    132		},
    133		{
    134			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
    135			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
    136			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
    137					- mmDPG_WATERMARK_MASK_CONTROL),
    138		},
    139		{
    140			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
    141			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
    142			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
    143					- mmDPG_WATERMARK_MASK_CONTROL),
    144		},
    145		{
    146			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
    147			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
    148			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
    149					- mmDPG_WATERMARK_MASK_CONTROL),
    150		}
    151};
    152
    153/* set register offset */
    154#define SR(reg_name)\
    155	.reg_name = mm ## reg_name
    156
    157/* set register offset with instance */
    158#define SRI(reg_name, block, id)\
    159	.reg_name = mm ## block ## id ## _ ## reg_name
    160
    161#define ipp_regs(id)\
    162[id] = {\
    163		IPP_COMMON_REG_LIST_DCE_BASE(id)\
    164}
    165
    166static const struct dce_ipp_registers ipp_regs[] = {
    167		ipp_regs(0),
    168		ipp_regs(1),
    169		ipp_regs(2),
    170		ipp_regs(3),
    171		ipp_regs(4),
    172		ipp_regs(5)
    173};
    174
    175static const struct dce_ipp_shift ipp_shift = {
    176		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
    177};
    178
    179static const struct dce_ipp_mask ipp_mask = {
    180		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
    181};
    182
    183#define transform_regs(id)\
    184[id] = {\
    185		XFM_COMMON_REG_LIST_DCE80(id)\
    186}
    187
    188static const struct dce_transform_registers xfm_regs[] = {
    189		transform_regs(0),
    190		transform_regs(1),
    191		transform_regs(2),
    192		transform_regs(3),
    193		transform_regs(4),
    194		transform_regs(5)
    195};
    196
    197static const struct dce_transform_shift xfm_shift = {
    198		XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
    199};
    200
    201static const struct dce_transform_mask xfm_mask = {
    202		XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
    203};
    204
    205#define aux_regs(id)\
    206[id] = {\
    207	AUX_REG_LIST(id)\
    208}
    209
    210static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
    211	aux_regs(0),
    212	aux_regs(1),
    213	aux_regs(2),
    214	aux_regs(3),
    215	aux_regs(4),
    216	aux_regs(5)
    217};
    218
    219#define hpd_regs(id)\
    220[id] = {\
    221	HPD_REG_LIST(id)\
    222}
    223
    224static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
    225		hpd_regs(0),
    226		hpd_regs(1),
    227		hpd_regs(2),
    228		hpd_regs(3),
    229		hpd_regs(4),
    230		hpd_regs(5)
    231};
    232
    233#define link_regs(id)\
    234[id] = {\
    235	LE_DCE80_REG_LIST(id)\
    236}
    237
    238static const struct dce110_link_enc_registers link_enc_regs[] = {
    239	link_regs(0),
    240	link_regs(1),
    241	link_regs(2),
    242	link_regs(3),
    243	link_regs(4),
    244	link_regs(5),
    245	link_regs(6),
    246};
    247
    248#define stream_enc_regs(id)\
    249[id] = {\
    250	SE_COMMON_REG_LIST_DCE_BASE(id),\
    251	.AFMT_CNTL = 0,\
    252}
    253
    254static const struct dce110_stream_enc_registers stream_enc_regs[] = {
    255	stream_enc_regs(0),
    256	stream_enc_regs(1),
    257	stream_enc_regs(2),
    258	stream_enc_regs(3),
    259	stream_enc_regs(4),
    260	stream_enc_regs(5),
    261	stream_enc_regs(6)
    262};
    263
    264static const struct dce_stream_encoder_shift se_shift = {
    265		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
    266};
    267
    268static const struct dce_stream_encoder_mask se_mask = {
    269		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
    270};
    271
    272static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
    273	{ DCE_PANEL_CNTL_REG_LIST() }
    274};
    275
    276static const struct dce_panel_cntl_shift panel_cntl_shift = {
    277	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
    278};
    279
    280static const struct dce_panel_cntl_mask panel_cntl_mask = {
    281	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
    282};
    283
    284#define opp_regs(id)\
    285[id] = {\
    286	OPP_DCE_80_REG_LIST(id),\
    287}
    288
    289static const struct dce_opp_registers opp_regs[] = {
    290	opp_regs(0),
    291	opp_regs(1),
    292	opp_regs(2),
    293	opp_regs(3),
    294	opp_regs(4),
    295	opp_regs(5)
    296};
    297
    298static const struct dce_opp_shift opp_shift = {
    299	OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
    300};
    301
    302static const struct dce_opp_mask opp_mask = {
    303	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
    304};
    305
    306static const struct dce110_aux_registers_shift aux_shift = {
    307	DCE10_AUX_MASK_SH_LIST(__SHIFT)
    308};
    309
    310static const struct dce110_aux_registers_mask aux_mask = {
    311	DCE10_AUX_MASK_SH_LIST(_MASK)
    312};
    313
    314#define aux_engine_regs(id)\
    315[id] = {\
    316	AUX_COMMON_REG_LIST(id), \
    317	.AUX_RESET_MASK = 0 \
    318}
    319
    320static const struct dce110_aux_registers aux_engine_regs[] = {
    321		aux_engine_regs(0),
    322		aux_engine_regs(1),
    323		aux_engine_regs(2),
    324		aux_engine_regs(3),
    325		aux_engine_regs(4),
    326		aux_engine_regs(5)
    327};
    328
    329#define audio_regs(id)\
    330[id] = {\
    331	AUD_COMMON_REG_LIST(id)\
    332}
    333
    334static const struct dce_audio_registers audio_regs[] = {
    335	audio_regs(0),
    336	audio_regs(1),
    337	audio_regs(2),
    338	audio_regs(3),
    339	audio_regs(4),
    340	audio_regs(5),
    341	audio_regs(6),
    342};
    343
    344static const struct dce_audio_shift audio_shift = {
    345		AUD_COMMON_MASK_SH_LIST(__SHIFT)
    346};
    347
    348static const struct dce_audio_mask audio_mask = {
    349		AUD_COMMON_MASK_SH_LIST(_MASK)
    350};
    351
    352#define clk_src_regs(id)\
    353[id] = {\
    354	CS_COMMON_REG_LIST_DCE_80(id),\
    355}
    356
    357
    358static const struct dce110_clk_src_regs clk_src_regs[] = {
    359	clk_src_regs(0),
    360	clk_src_regs(1),
    361	clk_src_regs(2)
    362};
    363
    364static const struct dce110_clk_src_shift cs_shift = {
    365		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
    366};
    367
    368static const struct dce110_clk_src_mask cs_mask = {
    369		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
    370};
    371
    372static const struct bios_registers bios_regs = {
    373	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
    374	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
    375};
    376
    377static const struct resource_caps res_cap = {
    378		.num_timing_generator = 6,
    379		.num_audio = 6,
    380		.num_stream_encoder = 6,
    381		.num_pll = 3,
    382		.num_ddc = 6,
    383};
    384
    385static const struct resource_caps res_cap_81 = {
    386		.num_timing_generator = 4,
    387		.num_audio = 7,
    388		.num_stream_encoder = 7,
    389		.num_pll = 3,
    390		.num_ddc = 6,
    391};
    392
    393static const struct resource_caps res_cap_83 = {
    394		.num_timing_generator = 2,
    395		.num_audio = 6,
    396		.num_stream_encoder = 6,
    397		.num_pll = 2,
    398		.num_ddc = 2,
    399};
    400
    401static const struct dc_plane_cap plane_cap = {
    402	.type = DC_PLANE_TYPE_DCE_RGB,
    403
    404	.pixel_format_support = {
    405			.argb8888 = true,
    406			.nv12 = false,
    407			.fp16 = true
    408	},
    409
    410	.max_upscale_factor = {
    411			.argb8888 = 16000,
    412			.nv12 = 1,
    413			.fp16 = 1
    414	},
    415
    416	.max_downscale_factor = {
    417			.argb8888 = 250,
    418			.nv12 = 1,
    419			.fp16 = 1
    420	}
    421};
    422
    423static const struct dce_dmcu_registers dmcu_regs = {
    424		DMCU_DCE80_REG_LIST()
    425};
    426
    427static const struct dce_dmcu_shift dmcu_shift = {
    428		DMCU_MASK_SH_LIST_DCE80(__SHIFT)
    429};
    430
    431static const struct dce_dmcu_mask dmcu_mask = {
    432		DMCU_MASK_SH_LIST_DCE80(_MASK)
    433};
    434static const struct dce_abm_registers abm_regs = {
    435		ABM_DCE110_COMMON_REG_LIST()
    436};
    437
    438static const struct dce_abm_shift abm_shift = {
    439		ABM_MASK_SH_LIST_DCE110(__SHIFT)
    440};
    441
    442static const struct dce_abm_mask abm_mask = {
    443		ABM_MASK_SH_LIST_DCE110(_MASK)
    444};
    445
    446#define CTX  ctx
    447#define REG(reg) mm ## reg
    448
    449#ifndef mmCC_DC_HDMI_STRAPS
    450#define mmCC_DC_HDMI_STRAPS 0x1918
    451#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
    452#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
    453#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
    454#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
    455#endif
    456
    457static int map_transmitter_id_to_phy_instance(
    458	enum transmitter transmitter)
    459{
    460	switch (transmitter) {
    461	case TRANSMITTER_UNIPHY_A:
    462		return 0;
    463	case TRANSMITTER_UNIPHY_B:
    464		return 1;
    465	case TRANSMITTER_UNIPHY_C:
    466		return 2;
    467	case TRANSMITTER_UNIPHY_D:
    468		return 3;
    469	case TRANSMITTER_UNIPHY_E:
    470		return 4;
    471	case TRANSMITTER_UNIPHY_F:
    472		return 5;
    473	case TRANSMITTER_UNIPHY_G:
    474		return 6;
    475	default:
    476		ASSERT(0);
    477		return 0;
    478	}
    479}
    480
    481static void read_dce_straps(
    482	struct dc_context *ctx,
    483	struct resource_straps *straps)
    484{
    485	REG_GET_2(CC_DC_HDMI_STRAPS,
    486			HDMI_DISABLE, &straps->hdmi_disable,
    487			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
    488
    489	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
    490}
    491
    492static struct audio *create_audio(
    493		struct dc_context *ctx, unsigned int inst)
    494{
    495	return dce_audio_create(ctx, inst,
    496			&audio_regs[inst], &audio_shift, &audio_mask);
    497}
    498
    499static struct timing_generator *dce80_timing_generator_create(
    500		struct dc_context *ctx,
    501		uint32_t instance,
    502		const struct dce110_timing_generator_offsets *offsets)
    503{
    504	struct dce110_timing_generator *tg110 =
    505		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
    506
    507	if (!tg110)
    508		return NULL;
    509
    510	dce80_timing_generator_construct(tg110, ctx, instance, offsets);
    511	return &tg110->base;
    512}
    513
    514static struct output_pixel_processor *dce80_opp_create(
    515	struct dc_context *ctx,
    516	uint32_t inst)
    517{
    518	struct dce110_opp *opp =
    519		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
    520
    521	if (!opp)
    522		return NULL;
    523
    524	dce110_opp_construct(opp,
    525			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
    526	return &opp->base;
    527}
    528
    529static struct dce_aux *dce80_aux_engine_create(
    530	struct dc_context *ctx,
    531	uint32_t inst)
    532{
    533	struct aux_engine_dce110 *aux_engine =
    534		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
    535
    536	if (!aux_engine)
    537		return NULL;
    538
    539	dce110_aux_engine_construct(aux_engine, ctx, inst,
    540				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
    541				    &aux_engine_regs[inst],
    542					&aux_mask,
    543					&aux_shift,
    544					ctx->dc->caps.extended_aux_timeout_support);
    545
    546	return &aux_engine->base;
    547}
    548#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
    549
    550static const struct dce_i2c_registers i2c_hw_regs[] = {
    551		i2c_inst_regs(1),
    552		i2c_inst_regs(2),
    553		i2c_inst_regs(3),
    554		i2c_inst_regs(4),
    555		i2c_inst_regs(5),
    556		i2c_inst_regs(6),
    557};
    558
    559static const struct dce_i2c_shift i2c_shifts = {
    560		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
    561};
    562
    563static const struct dce_i2c_mask i2c_masks = {
    564		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
    565};
    566
    567static struct dce_i2c_hw *dce80_i2c_hw_create(
    568	struct dc_context *ctx,
    569	uint32_t inst)
    570{
    571	struct dce_i2c_hw *dce_i2c_hw =
    572		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
    573
    574	if (!dce_i2c_hw)
    575		return NULL;
    576
    577	dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
    578				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
    579
    580	return dce_i2c_hw;
    581}
    582
    583static struct dce_i2c_sw *dce80_i2c_sw_create(
    584	struct dc_context *ctx)
    585{
    586	struct dce_i2c_sw *dce_i2c_sw =
    587		kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
    588
    589	if (!dce_i2c_sw)
    590		return NULL;
    591
    592	dce_i2c_sw_construct(dce_i2c_sw, ctx);
    593
    594	return dce_i2c_sw;
    595}
    596static struct stream_encoder *dce80_stream_encoder_create(
    597	enum engine_id eng_id,
    598	struct dc_context *ctx)
    599{
    600	struct dce110_stream_encoder *enc110 =
    601		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
    602
    603	if (!enc110)
    604		return NULL;
    605
    606	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
    607					&stream_enc_regs[eng_id],
    608					&se_shift, &se_mask);
    609	return &enc110->base;
    610}
    611
    612#define SRII(reg_name, block, id)\
    613	.reg_name[id] = mm ## block ## id ## _ ## reg_name
    614
    615static const struct dce_hwseq_registers hwseq_reg = {
    616		HWSEQ_DCE8_REG_LIST()
    617};
    618
    619static const struct dce_hwseq_shift hwseq_shift = {
    620		HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
    621};
    622
    623static const struct dce_hwseq_mask hwseq_mask = {
    624		HWSEQ_DCE8_MASK_SH_LIST(_MASK)
    625};
    626
    627static struct dce_hwseq *dce80_hwseq_create(
    628	struct dc_context *ctx)
    629{
    630	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
    631
    632	if (hws) {
    633		hws->ctx = ctx;
    634		hws->regs = &hwseq_reg;
    635		hws->shifts = &hwseq_shift;
    636		hws->masks = &hwseq_mask;
    637	}
    638	return hws;
    639}
    640
    641static const struct resource_create_funcs res_create_funcs = {
    642	.read_dce_straps = read_dce_straps,
    643	.create_audio = create_audio,
    644	.create_stream_encoder = dce80_stream_encoder_create,
    645	.create_hwseq = dce80_hwseq_create,
    646};
    647
    648#define mi_inst_regs(id) { \
    649	MI_DCE8_REG_LIST(id), \
    650	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
    651}
    652static const struct dce_mem_input_registers mi_regs[] = {
    653		mi_inst_regs(0),
    654		mi_inst_regs(1),
    655		mi_inst_regs(2),
    656		mi_inst_regs(3),
    657		mi_inst_regs(4),
    658		mi_inst_regs(5),
    659};
    660
    661static const struct dce_mem_input_shift mi_shifts = {
    662		MI_DCE8_MASK_SH_LIST(__SHIFT),
    663		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
    664};
    665
    666static const struct dce_mem_input_mask mi_masks = {
    667		MI_DCE8_MASK_SH_LIST(_MASK),
    668		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
    669};
    670
    671static struct mem_input *dce80_mem_input_create(
    672	struct dc_context *ctx,
    673	uint32_t inst)
    674{
    675	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
    676					       GFP_KERNEL);
    677
    678	if (!dce_mi) {
    679		BREAK_TO_DEBUGGER();
    680		return NULL;
    681	}
    682
    683	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
    684	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
    685	return &dce_mi->base;
    686}
    687
    688static void dce80_transform_destroy(struct transform **xfm)
    689{
    690	kfree(TO_DCE_TRANSFORM(*xfm));
    691	*xfm = NULL;
    692}
    693
    694static struct transform *dce80_transform_create(
    695	struct dc_context *ctx,
    696	uint32_t inst)
    697{
    698	struct dce_transform *transform =
    699		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
    700
    701	if (!transform)
    702		return NULL;
    703
    704	dce_transform_construct(transform, ctx, inst,
    705				&xfm_regs[inst], &xfm_shift, &xfm_mask);
    706	transform->prescaler_on = false;
    707	return &transform->base;
    708}
    709
    710static const struct encoder_feature_support link_enc_feature = {
    711		.max_hdmi_deep_color = COLOR_DEPTH_121212,
    712		.max_hdmi_pixel_clock = 297000,
    713		.flags.bits.IS_HBR2_CAPABLE = true,
    714		.flags.bits.IS_TPS3_CAPABLE = true
    715};
    716
    717static struct link_encoder *dce80_link_encoder_create(
    718	const struct encoder_init_data *enc_init_data)
    719{
    720	struct dce110_link_encoder *enc110 =
    721		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
    722	int link_regs_id;
    723
    724	if (!enc110)
    725		return NULL;
    726
    727	link_regs_id =
    728		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
    729
    730	dce110_link_encoder_construct(enc110,
    731				      enc_init_data,
    732				      &link_enc_feature,
    733				      &link_enc_regs[link_regs_id],
    734				      &link_enc_aux_regs[enc_init_data->channel - 1],
    735				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
    736	return &enc110->base;
    737}
    738
    739static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
    740{
    741	struct dce_panel_cntl *panel_cntl =
    742		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
    743
    744	if (!panel_cntl)
    745		return NULL;
    746
    747	dce_panel_cntl_construct(panel_cntl,
    748			init_data,
    749			&panel_cntl_regs[init_data->inst],
    750			&panel_cntl_shift,
    751			&panel_cntl_mask);
    752
    753	return &panel_cntl->base;
    754}
    755
    756static struct clock_source *dce80_clock_source_create(
    757	struct dc_context *ctx,
    758	struct dc_bios *bios,
    759	enum clock_source_id id,
    760	const struct dce110_clk_src_regs *regs,
    761	bool dp_clk_src)
    762{
    763	struct dce110_clk_src *clk_src =
    764		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
    765
    766	if (!clk_src)
    767		return NULL;
    768
    769	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
    770			regs, &cs_shift, &cs_mask)) {
    771		clk_src->base.dp_clk_src = dp_clk_src;
    772		return &clk_src->base;
    773	}
    774
    775	kfree(clk_src);
    776	BREAK_TO_DEBUGGER();
    777	return NULL;
    778}
    779
    780static void dce80_clock_source_destroy(struct clock_source **clk_src)
    781{
    782	kfree(TO_DCE110_CLK_SRC(*clk_src));
    783	*clk_src = NULL;
    784}
    785
    786static struct input_pixel_processor *dce80_ipp_create(
    787	struct dc_context *ctx, uint32_t inst)
    788{
    789	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
    790
    791	if (!ipp) {
    792		BREAK_TO_DEBUGGER();
    793		return NULL;
    794	}
    795
    796	dce_ipp_construct(ipp, ctx, inst,
    797			&ipp_regs[inst], &ipp_shift, &ipp_mask);
    798	return &ipp->base;
    799}
    800
    801static void dce80_resource_destruct(struct dce110_resource_pool *pool)
    802{
    803	unsigned int i;
    804
    805	for (i = 0; i < pool->base.pipe_count; i++) {
    806		if (pool->base.opps[i] != NULL)
    807			dce110_opp_destroy(&pool->base.opps[i]);
    808
    809		if (pool->base.transforms[i] != NULL)
    810			dce80_transform_destroy(&pool->base.transforms[i]);
    811
    812		if (pool->base.ipps[i] != NULL)
    813			dce_ipp_destroy(&pool->base.ipps[i]);
    814
    815		if (pool->base.mis[i] != NULL) {
    816			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
    817			pool->base.mis[i] = NULL;
    818		}
    819
    820		if (pool->base.timing_generators[i] != NULL)	{
    821			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
    822			pool->base.timing_generators[i] = NULL;
    823		}
    824	}
    825
    826	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
    827		if (pool->base.engines[i] != NULL)
    828			dce110_engine_destroy(&pool->base.engines[i]);
    829		if (pool->base.hw_i2cs[i] != NULL) {
    830			kfree(pool->base.hw_i2cs[i]);
    831			pool->base.hw_i2cs[i] = NULL;
    832		}
    833		if (pool->base.sw_i2cs[i] != NULL) {
    834			kfree(pool->base.sw_i2cs[i]);
    835			pool->base.sw_i2cs[i] = NULL;
    836		}
    837	}
    838
    839	for (i = 0; i < pool->base.stream_enc_count; i++) {
    840		if (pool->base.stream_enc[i] != NULL)
    841			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
    842	}
    843
    844	for (i = 0; i < pool->base.clk_src_count; i++) {
    845		if (pool->base.clock_sources[i] != NULL) {
    846			dce80_clock_source_destroy(&pool->base.clock_sources[i]);
    847		}
    848	}
    849
    850	if (pool->base.abm != NULL)
    851			dce_abm_destroy(&pool->base.abm);
    852
    853	if (pool->base.dmcu != NULL)
    854			dce_dmcu_destroy(&pool->base.dmcu);
    855
    856	if (pool->base.dp_clock_source != NULL)
    857		dce80_clock_source_destroy(&pool->base.dp_clock_source);
    858
    859	for (i = 0; i < pool->base.audio_count; i++)	{
    860		if (pool->base.audios[i] != NULL) {
    861			dce_aud_destroy(&pool->base.audios[i]);
    862		}
    863	}
    864
    865	if (pool->base.irqs != NULL) {
    866		dal_irq_service_destroy(&pool->base.irqs);
    867	}
    868}
    869
    870static bool dce80_validate_bandwidth(
    871	struct dc *dc,
    872	struct dc_state *context,
    873	bool fast_validate)
    874{
    875	int i;
    876	bool at_least_one_pipe = false;
    877
    878	for (i = 0; i < dc->res_pool->pipe_count; i++) {
    879		if (context->res_ctx.pipe_ctx[i].stream)
    880			at_least_one_pipe = true;
    881	}
    882
    883	if (at_least_one_pipe) {
    884		/* TODO implement when needed but for now hardcode max value*/
    885		context->bw_ctx.bw.dce.dispclk_khz = 681000;
    886		context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
    887	} else {
    888		context->bw_ctx.bw.dce.dispclk_khz = 0;
    889		context->bw_ctx.bw.dce.yclk_khz = 0;
    890	}
    891
    892	return true;
    893}
    894
    895static bool dce80_validate_surface_sets(
    896		struct dc_state *context)
    897{
    898	int i;
    899
    900	for (i = 0; i < context->stream_count; i++) {
    901		if (context->stream_status[i].plane_count == 0)
    902			continue;
    903
    904		if (context->stream_status[i].plane_count > 1)
    905			return false;
    906
    907		if (context->stream_status[i].plane_states[0]->format
    908				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
    909			return false;
    910	}
    911
    912	return true;
    913}
    914
    915static enum dc_status dce80_validate_global(
    916		struct dc *dc,
    917		struct dc_state *context)
    918{
    919	if (!dce80_validate_surface_sets(context))
    920		return DC_FAIL_SURFACE_VALIDATE;
    921
    922	return DC_OK;
    923}
    924
    925static void dce80_destroy_resource_pool(struct resource_pool **pool)
    926{
    927	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
    928
    929	dce80_resource_destruct(dce110_pool);
    930	kfree(dce110_pool);
    931	*pool = NULL;
    932}
    933
    934static const struct resource_funcs dce80_res_pool_funcs = {
    935	.destroy = dce80_destroy_resource_pool,
    936	.link_enc_create = dce80_link_encoder_create,
    937	.panel_cntl_create = dce80_panel_cntl_create,
    938	.validate_bandwidth = dce80_validate_bandwidth,
    939	.validate_plane = dce100_validate_plane,
    940	.add_stream_to_ctx = dce100_add_stream_to_ctx,
    941	.validate_global = dce80_validate_global,
    942	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
    943};
    944
    945static bool dce80_construct(
    946	uint8_t num_virtual_links,
    947	struct dc *dc,
    948	struct dce110_resource_pool *pool)
    949{
    950	unsigned int i;
    951	struct dc_context *ctx = dc->ctx;
    952	struct dc_bios *bp;
    953
    954	ctx->dc_bios->regs = &bios_regs;
    955
    956	pool->base.res_cap = &res_cap;
    957	pool->base.funcs = &dce80_res_pool_funcs;
    958
    959
    960	/*************************************************
    961	 *  Resource + asic cap harcoding                *
    962	 *************************************************/
    963	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
    964	pool->base.pipe_count = res_cap.num_timing_generator;
    965	pool->base.timing_generator_count = res_cap.num_timing_generator;
    966	dc->caps.max_downscale_ratio = 200;
    967	dc->caps.i2c_speed_in_khz = 40;
    968	dc->caps.i2c_speed_in_khz_hdcp = 40;
    969	dc->caps.max_cursor_size = 128;
    970	dc->caps.min_horizontal_blanking_period = 80;
    971	dc->caps.dual_link_dvi = true;
    972	dc->caps.extended_aux_timeout_support = false;
    973
    974	/*************************************************
    975	 *  Create resources                             *
    976	 *************************************************/
    977
    978	bp = ctx->dc_bios;
    979
    980	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
    981		pool->base.dp_clock_source =
    982				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
    983
    984		pool->base.clock_sources[0] =
    985				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
    986		pool->base.clock_sources[1] =
    987				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
    988		pool->base.clock_sources[2] =
    989				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
    990		pool->base.clk_src_count = 3;
    991
    992	} else {
    993		pool->base.dp_clock_source =
    994				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
    995
    996		pool->base.clock_sources[0] =
    997				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
    998		pool->base.clock_sources[1] =
    999				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
   1000		pool->base.clk_src_count = 2;
   1001	}
   1002
   1003	if (pool->base.dp_clock_source == NULL) {
   1004		dm_error("DC: failed to create dp clock source!\n");
   1005		BREAK_TO_DEBUGGER();
   1006		goto res_create_fail;
   1007	}
   1008
   1009	for (i = 0; i < pool->base.clk_src_count; i++) {
   1010		if (pool->base.clock_sources[i] == NULL) {
   1011			dm_error("DC: failed to create clock sources!\n");
   1012			BREAK_TO_DEBUGGER();
   1013			goto res_create_fail;
   1014		}
   1015	}
   1016
   1017	pool->base.dmcu = dce_dmcu_create(ctx,
   1018			&dmcu_regs,
   1019			&dmcu_shift,
   1020			&dmcu_mask);
   1021	if (pool->base.dmcu == NULL) {
   1022		dm_error("DC: failed to create dmcu!\n");
   1023		BREAK_TO_DEBUGGER();
   1024		goto res_create_fail;
   1025	}
   1026
   1027	pool->base.abm = dce_abm_create(ctx,
   1028			&abm_regs,
   1029			&abm_shift,
   1030			&abm_mask);
   1031	if (pool->base.abm == NULL) {
   1032		dm_error("DC: failed to create abm!\n");
   1033		BREAK_TO_DEBUGGER();
   1034		goto res_create_fail;
   1035	}
   1036
   1037	{
   1038		struct irq_service_init_data init_data;
   1039		init_data.ctx = dc->ctx;
   1040		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
   1041		if (!pool->base.irqs)
   1042			goto res_create_fail;
   1043	}
   1044
   1045	for (i = 0; i < pool->base.pipe_count; i++) {
   1046		pool->base.timing_generators[i] = dce80_timing_generator_create(
   1047				ctx, i, &dce80_tg_offsets[i]);
   1048		if (pool->base.timing_generators[i] == NULL) {
   1049			BREAK_TO_DEBUGGER();
   1050			dm_error("DC: failed to create tg!\n");
   1051			goto res_create_fail;
   1052		}
   1053
   1054		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
   1055		if (pool->base.mis[i] == NULL) {
   1056			BREAK_TO_DEBUGGER();
   1057			dm_error("DC: failed to create memory input!\n");
   1058			goto res_create_fail;
   1059		}
   1060
   1061		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
   1062		if (pool->base.ipps[i] == NULL) {
   1063			BREAK_TO_DEBUGGER();
   1064			dm_error("DC: failed to create input pixel processor!\n");
   1065			goto res_create_fail;
   1066		}
   1067
   1068		pool->base.transforms[i] = dce80_transform_create(ctx, i);
   1069		if (pool->base.transforms[i] == NULL) {
   1070			BREAK_TO_DEBUGGER();
   1071			dm_error("DC: failed to create transform!\n");
   1072			goto res_create_fail;
   1073		}
   1074
   1075		pool->base.opps[i] = dce80_opp_create(ctx, i);
   1076		if (pool->base.opps[i] == NULL) {
   1077			BREAK_TO_DEBUGGER();
   1078			dm_error("DC: failed to create output pixel processor!\n");
   1079			goto res_create_fail;
   1080		}
   1081	}
   1082
   1083	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
   1084		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
   1085		if (pool->base.engines[i] == NULL) {
   1086			BREAK_TO_DEBUGGER();
   1087			dm_error(
   1088				"DC:failed to create aux engine!!\n");
   1089			goto res_create_fail;
   1090		}
   1091		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
   1092		if (pool->base.hw_i2cs[i] == NULL) {
   1093			BREAK_TO_DEBUGGER();
   1094			dm_error(
   1095				"DC:failed to create i2c engine!!\n");
   1096			goto res_create_fail;
   1097		}
   1098		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
   1099		if (pool->base.sw_i2cs[i] == NULL) {
   1100			BREAK_TO_DEBUGGER();
   1101			dm_error(
   1102				"DC:failed to create sw i2c!!\n");
   1103			goto res_create_fail;
   1104		}
   1105	}
   1106
   1107	dc->caps.max_planes =  pool->base.pipe_count;
   1108
   1109	for (i = 0; i < dc->caps.max_planes; ++i)
   1110		dc->caps.planes[i] = plane_cap;
   1111
   1112	dc->caps.disable_dp_clk_share = true;
   1113
   1114	if (!resource_construct(num_virtual_links, dc, &pool->base,
   1115			&res_create_funcs))
   1116		goto res_create_fail;
   1117
   1118	/* Create hardware sequencer */
   1119	dce80_hw_sequencer_construct(dc);
   1120
   1121	return true;
   1122
   1123res_create_fail:
   1124	dce80_resource_destruct(pool);
   1125	return false;
   1126}
   1127
   1128struct resource_pool *dce80_create_resource_pool(
   1129	uint8_t num_virtual_links,
   1130	struct dc *dc)
   1131{
   1132	struct dce110_resource_pool *pool =
   1133		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
   1134
   1135	if (!pool)
   1136		return NULL;
   1137
   1138	if (dce80_construct(num_virtual_links, dc, pool))
   1139		return &pool->base;
   1140
   1141	BREAK_TO_DEBUGGER();
   1142	return NULL;
   1143}
   1144
   1145static bool dce81_construct(
   1146	uint8_t num_virtual_links,
   1147	struct dc *dc,
   1148	struct dce110_resource_pool *pool)
   1149{
   1150	unsigned int i;
   1151	struct dc_context *ctx = dc->ctx;
   1152	struct dc_bios *bp;
   1153
   1154	ctx->dc_bios->regs = &bios_regs;
   1155
   1156	pool->base.res_cap = &res_cap_81;
   1157	pool->base.funcs = &dce80_res_pool_funcs;
   1158
   1159
   1160	/*************************************************
   1161	 *  Resource + asic cap harcoding                *
   1162	 *************************************************/
   1163	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
   1164	pool->base.pipe_count = res_cap_81.num_timing_generator;
   1165	pool->base.timing_generator_count = res_cap_81.num_timing_generator;
   1166	dc->caps.max_downscale_ratio = 200;
   1167	dc->caps.i2c_speed_in_khz = 40;
   1168	dc->caps.i2c_speed_in_khz_hdcp = 40;
   1169	dc->caps.max_cursor_size = 128;
   1170	dc->caps.min_horizontal_blanking_period = 80;
   1171	dc->caps.is_apu = true;
   1172
   1173	/*************************************************
   1174	 *  Create resources                             *
   1175	 *************************************************/
   1176
   1177	bp = ctx->dc_bios;
   1178
   1179	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
   1180		pool->base.dp_clock_source =
   1181				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
   1182
   1183		pool->base.clock_sources[0] =
   1184				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
   1185		pool->base.clock_sources[1] =
   1186				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
   1187		pool->base.clock_sources[2] =
   1188				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
   1189		pool->base.clk_src_count = 3;
   1190
   1191	} else {
   1192		pool->base.dp_clock_source =
   1193				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
   1194
   1195		pool->base.clock_sources[0] =
   1196				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
   1197		pool->base.clock_sources[1] =
   1198				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
   1199		pool->base.clk_src_count = 2;
   1200	}
   1201
   1202	if (pool->base.dp_clock_source == NULL) {
   1203		dm_error("DC: failed to create dp clock source!\n");
   1204		BREAK_TO_DEBUGGER();
   1205		goto res_create_fail;
   1206	}
   1207
   1208	for (i = 0; i < pool->base.clk_src_count; i++) {
   1209		if (pool->base.clock_sources[i] == NULL) {
   1210			dm_error("DC: failed to create clock sources!\n");
   1211			BREAK_TO_DEBUGGER();
   1212			goto res_create_fail;
   1213		}
   1214	}
   1215
   1216	pool->base.dmcu = dce_dmcu_create(ctx,
   1217			&dmcu_regs,
   1218			&dmcu_shift,
   1219			&dmcu_mask);
   1220	if (pool->base.dmcu == NULL) {
   1221		dm_error("DC: failed to create dmcu!\n");
   1222		BREAK_TO_DEBUGGER();
   1223		goto res_create_fail;
   1224	}
   1225
   1226	pool->base.abm = dce_abm_create(ctx,
   1227			&abm_regs,
   1228			&abm_shift,
   1229			&abm_mask);
   1230	if (pool->base.abm == NULL) {
   1231		dm_error("DC: failed to create abm!\n");
   1232		BREAK_TO_DEBUGGER();
   1233		goto res_create_fail;
   1234	}
   1235
   1236	{
   1237		struct irq_service_init_data init_data;
   1238		init_data.ctx = dc->ctx;
   1239		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
   1240		if (!pool->base.irqs)
   1241			goto res_create_fail;
   1242	}
   1243
   1244	for (i = 0; i < pool->base.pipe_count; i++) {
   1245		pool->base.timing_generators[i] = dce80_timing_generator_create(
   1246				ctx, i, &dce80_tg_offsets[i]);
   1247		if (pool->base.timing_generators[i] == NULL) {
   1248			BREAK_TO_DEBUGGER();
   1249			dm_error("DC: failed to create tg!\n");
   1250			goto res_create_fail;
   1251		}
   1252
   1253		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
   1254		if (pool->base.mis[i] == NULL) {
   1255			BREAK_TO_DEBUGGER();
   1256			dm_error("DC: failed to create memory input!\n");
   1257			goto res_create_fail;
   1258		}
   1259
   1260		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
   1261		if (pool->base.ipps[i] == NULL) {
   1262			BREAK_TO_DEBUGGER();
   1263			dm_error("DC: failed to create input pixel processor!\n");
   1264			goto res_create_fail;
   1265		}
   1266
   1267		pool->base.transforms[i] = dce80_transform_create(ctx, i);
   1268		if (pool->base.transforms[i] == NULL) {
   1269			BREAK_TO_DEBUGGER();
   1270			dm_error("DC: failed to create transform!\n");
   1271			goto res_create_fail;
   1272		}
   1273
   1274		pool->base.opps[i] = dce80_opp_create(ctx, i);
   1275		if (pool->base.opps[i] == NULL) {
   1276			BREAK_TO_DEBUGGER();
   1277			dm_error("DC: failed to create output pixel processor!\n");
   1278			goto res_create_fail;
   1279		}
   1280	}
   1281
   1282	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
   1283		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
   1284		if (pool->base.engines[i] == NULL) {
   1285			BREAK_TO_DEBUGGER();
   1286			dm_error(
   1287				"DC:failed to create aux engine!!\n");
   1288			goto res_create_fail;
   1289		}
   1290		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
   1291		if (pool->base.hw_i2cs[i] == NULL) {
   1292			BREAK_TO_DEBUGGER();
   1293			dm_error(
   1294				"DC:failed to create i2c engine!!\n");
   1295			goto res_create_fail;
   1296		}
   1297		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
   1298		if (pool->base.sw_i2cs[i] == NULL) {
   1299			BREAK_TO_DEBUGGER();
   1300			dm_error(
   1301				"DC:failed to create sw i2c!!\n");
   1302			goto res_create_fail;
   1303		}
   1304	}
   1305
   1306	dc->caps.max_planes =  pool->base.pipe_count;
   1307
   1308	for (i = 0; i < dc->caps.max_planes; ++i)
   1309		dc->caps.planes[i] = plane_cap;
   1310
   1311	dc->caps.disable_dp_clk_share = true;
   1312
   1313	if (!resource_construct(num_virtual_links, dc, &pool->base,
   1314			&res_create_funcs))
   1315		goto res_create_fail;
   1316
   1317	/* Create hardware sequencer */
   1318	dce80_hw_sequencer_construct(dc);
   1319
   1320	return true;
   1321
   1322res_create_fail:
   1323	dce80_resource_destruct(pool);
   1324	return false;
   1325}
   1326
   1327struct resource_pool *dce81_create_resource_pool(
   1328	uint8_t num_virtual_links,
   1329	struct dc *dc)
   1330{
   1331	struct dce110_resource_pool *pool =
   1332		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
   1333
   1334	if (!pool)
   1335		return NULL;
   1336
   1337	if (dce81_construct(num_virtual_links, dc, pool))
   1338		return &pool->base;
   1339
   1340	BREAK_TO_DEBUGGER();
   1341	return NULL;
   1342}
   1343
   1344static bool dce83_construct(
   1345	uint8_t num_virtual_links,
   1346	struct dc *dc,
   1347	struct dce110_resource_pool *pool)
   1348{
   1349	unsigned int i;
   1350	struct dc_context *ctx = dc->ctx;
   1351	struct dc_bios *bp;
   1352
   1353	ctx->dc_bios->regs = &bios_regs;
   1354
   1355	pool->base.res_cap = &res_cap_83;
   1356	pool->base.funcs = &dce80_res_pool_funcs;
   1357
   1358
   1359	/*************************************************
   1360	 *  Resource + asic cap harcoding                *
   1361	 *************************************************/
   1362	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
   1363	pool->base.pipe_count = res_cap_83.num_timing_generator;
   1364	pool->base.timing_generator_count = res_cap_83.num_timing_generator;
   1365	dc->caps.max_downscale_ratio = 200;
   1366	dc->caps.i2c_speed_in_khz = 40;
   1367	dc->caps.i2c_speed_in_khz_hdcp = 40;
   1368	dc->caps.max_cursor_size = 128;
   1369	dc->caps.min_horizontal_blanking_period = 80;
   1370	dc->caps.is_apu = true;
   1371
   1372	/*************************************************
   1373	 *  Create resources                             *
   1374	 *************************************************/
   1375
   1376	bp = ctx->dc_bios;
   1377
   1378	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
   1379		pool->base.dp_clock_source =
   1380				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
   1381
   1382		pool->base.clock_sources[0] =
   1383				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
   1384		pool->base.clock_sources[1] =
   1385				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
   1386		pool->base.clk_src_count = 2;
   1387
   1388	} else {
   1389		pool->base.dp_clock_source =
   1390				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
   1391
   1392		pool->base.clock_sources[0] =
   1393				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
   1394		pool->base.clk_src_count = 1;
   1395	}
   1396
   1397	if (pool->base.dp_clock_source == NULL) {
   1398		dm_error("DC: failed to create dp clock source!\n");
   1399		BREAK_TO_DEBUGGER();
   1400		goto res_create_fail;
   1401	}
   1402
   1403	for (i = 0; i < pool->base.clk_src_count; i++) {
   1404		if (pool->base.clock_sources[i] == NULL) {
   1405			dm_error("DC: failed to create clock sources!\n");
   1406			BREAK_TO_DEBUGGER();
   1407			goto res_create_fail;
   1408		}
   1409	}
   1410
   1411	pool->base.dmcu = dce_dmcu_create(ctx,
   1412			&dmcu_regs,
   1413			&dmcu_shift,
   1414			&dmcu_mask);
   1415	if (pool->base.dmcu == NULL) {
   1416		dm_error("DC: failed to create dmcu!\n");
   1417		BREAK_TO_DEBUGGER();
   1418		goto res_create_fail;
   1419	}
   1420
   1421	pool->base.abm = dce_abm_create(ctx,
   1422			&abm_regs,
   1423			&abm_shift,
   1424			&abm_mask);
   1425	if (pool->base.abm == NULL) {
   1426		dm_error("DC: failed to create abm!\n");
   1427		BREAK_TO_DEBUGGER();
   1428		goto res_create_fail;
   1429	}
   1430
   1431	{
   1432		struct irq_service_init_data init_data;
   1433		init_data.ctx = dc->ctx;
   1434		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
   1435		if (!pool->base.irqs)
   1436			goto res_create_fail;
   1437	}
   1438
   1439	for (i = 0; i < pool->base.pipe_count; i++) {
   1440		pool->base.timing_generators[i] = dce80_timing_generator_create(
   1441				ctx, i, &dce80_tg_offsets[i]);
   1442		if (pool->base.timing_generators[i] == NULL) {
   1443			BREAK_TO_DEBUGGER();
   1444			dm_error("DC: failed to create tg!\n");
   1445			goto res_create_fail;
   1446		}
   1447
   1448		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
   1449		if (pool->base.mis[i] == NULL) {
   1450			BREAK_TO_DEBUGGER();
   1451			dm_error("DC: failed to create memory input!\n");
   1452			goto res_create_fail;
   1453		}
   1454
   1455		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
   1456		if (pool->base.ipps[i] == NULL) {
   1457			BREAK_TO_DEBUGGER();
   1458			dm_error("DC: failed to create input pixel processor!\n");
   1459			goto res_create_fail;
   1460		}
   1461
   1462		pool->base.transforms[i] = dce80_transform_create(ctx, i);
   1463		if (pool->base.transforms[i] == NULL) {
   1464			BREAK_TO_DEBUGGER();
   1465			dm_error("DC: failed to create transform!\n");
   1466			goto res_create_fail;
   1467		}
   1468
   1469		pool->base.opps[i] = dce80_opp_create(ctx, i);
   1470		if (pool->base.opps[i] == NULL) {
   1471			BREAK_TO_DEBUGGER();
   1472			dm_error("DC: failed to create output pixel processor!\n");
   1473			goto res_create_fail;
   1474		}
   1475	}
   1476
   1477	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
   1478		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
   1479		if (pool->base.engines[i] == NULL) {
   1480			BREAK_TO_DEBUGGER();
   1481			dm_error(
   1482				"DC:failed to create aux engine!!\n");
   1483			goto res_create_fail;
   1484		}
   1485		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
   1486		if (pool->base.hw_i2cs[i] == NULL) {
   1487			BREAK_TO_DEBUGGER();
   1488			dm_error(
   1489				"DC:failed to create i2c engine!!\n");
   1490			goto res_create_fail;
   1491		}
   1492		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
   1493		if (pool->base.sw_i2cs[i] == NULL) {
   1494			BREAK_TO_DEBUGGER();
   1495			dm_error(
   1496				"DC:failed to create sw i2c!!\n");
   1497			goto res_create_fail;
   1498		}
   1499	}
   1500
   1501	dc->caps.max_planes =  pool->base.pipe_count;
   1502
   1503	for (i = 0; i < dc->caps.max_planes; ++i)
   1504		dc->caps.planes[i] = plane_cap;
   1505
   1506	dc->caps.disable_dp_clk_share = true;
   1507
   1508	if (!resource_construct(num_virtual_links, dc, &pool->base,
   1509			&res_create_funcs))
   1510		goto res_create_fail;
   1511
   1512	/* Create hardware sequencer */
   1513	dce80_hw_sequencer_construct(dc);
   1514
   1515	return true;
   1516
   1517res_create_fail:
   1518	dce80_resource_destruct(pool);
   1519	return false;
   1520}
   1521
   1522struct resource_pool *dce83_create_resource_pool(
   1523	uint8_t num_virtual_links,
   1524	struct dc *dc)
   1525{
   1526	struct dce110_resource_pool *pool =
   1527		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
   1528
   1529	if (!pool)
   1530		return NULL;
   1531
   1532	if (dce83_construct(num_virtual_links, dc, pool))
   1533		return &pool->base;
   1534
   1535	BREAK_TO_DEBUGGER();
   1536	return NULL;
   1537}