dcn10_dpp.h (65330B)
1/* Copyright 2016 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25#ifndef __DAL_DPP_DCN10_H__ 26#define __DAL_DPP_DCN10_H__ 27 28#include "dpp.h" 29 30#define TO_DCN10_DPP(dpp)\ 31 container_of(dpp, struct dcn10_dpp, base) 32 33/* TODO: Use correct number of taps. Using polaris values for now */ 34#define LB_TOTAL_NUMBER_OF_ENTRIES 5124 35#define LB_BITS_PER_ENTRY 144 36 37#define TF_SF(reg_name, field_name, post_fix)\ 38 .field_name = reg_name ## __ ## field_name ## post_fix 39 40//Used to resolve corner case 41#define TF2_SF(reg_name, field_name, post_fix)\ 42 .field_name = reg_name ## _ ## field_name ## post_fix 43 44#define TF_REG_LIST_DCN(id) \ 45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ 46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ 47 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\ 48 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\ 49 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\ 50 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\ 51 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ 52 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ 53 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ 54 SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \ 55 SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \ 56 SRI(OTG_H_BLANK, DSCL, id), \ 57 SRI(OTG_V_BLANK, DSCL, id), \ 58 SRI(SCL_MODE, DSCL, id), \ 59 SRI(LB_DATA_FORMAT, DSCL, id), \ 60 SRI(LB_MEMORY_CTRL, DSCL, id), \ 61 SRI(DSCL_AUTOCAL, DSCL, id), \ 62 SRI(SCL_BLACK_OFFSET, DSCL, id), \ 63 SRI(SCL_TAP_CONTROL, DSCL, id), \ 64 SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ 65 SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ 66 SRI(DSCL_2TAP_CONTROL, DSCL, id), \ 67 SRI(MPC_SIZE, DSCL, id), \ 68 SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ 69 SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ 70 SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ 71 SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ 72 SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \ 73 SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ 74 SRI(SCL_VERT_FILTER_INIT, DSCL, id), \ 75 SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \ 76 SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \ 77 SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ 78 SRI(RECOUT_START, DSCL, id), \ 79 SRI(RECOUT_SIZE, DSCL, id), \ 80 SRI(CM_ICSC_CONTROL, CM, id), \ 81 SRI(CM_ICSC_C11_C12, CM, id), \ 82 SRI(CM_ICSC_C33_C34, CM, id), \ 83 SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ 84 SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ 85 SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ 86 SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 87 SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 88 SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 89 SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ 90 SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ 91 SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ 92 SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ 93 SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ 94 SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ 95 SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ 96 SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ 97 SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ 98 SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ 99 SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ 100 SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ 101 SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ 102 SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ 103 SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ 104 SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ 105 SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ 106 SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ 107 SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ 108 SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ 109 SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ 110 SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ 111 SRI(CM_MEM_PWR_CTRL, CM, id), \ 112 SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ 113 SRI(CM_DGAM_LUT_INDEX, CM, id), \ 114 SRI(CM_DGAM_LUT_DATA, CM, id), \ 115 SRI(CM_CONTROL, CM, id), \ 116 SRI(CM_DGAM_CONTROL, CM, id), \ 117 SRI(CM_TEST_DEBUG_INDEX, CM, id), \ 118 SRI(CM_TEST_DEBUG_DATA, CM, id), \ 119 SRI(FORMAT_CONTROL, CNVC_CFG, id), \ 120 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 121 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ 122 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ 123 SRI(CURSOR0_COLOR1, CNVC_CUR, id), \ 124 SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \ 125 SRI(DPP_CONTROL, DPP_TOP, id), \ 126 SRI(CM_HDR_MULT_COEF, CM, id) 127 128 129 130#define TF_REG_LIST_DCN10(id) \ 131 TF_REG_LIST_DCN(id), \ 132 SRI(CM_COMA_C11_C12, CM, id),\ 133 SRI(CM_COMA_C33_C34, CM, id),\ 134 SRI(CM_COMB_C11_C12, CM, id),\ 135 SRI(CM_COMB_C33_C34, CM, id),\ 136 SRI(CM_OCSC_CONTROL, CM, id), \ 137 SRI(CM_OCSC_C11_C12, CM, id), \ 138 SRI(CM_OCSC_C33_C34, CM, id), \ 139 SRI(CM_BNS_VALUES_R, CM, id), \ 140 SRI(CM_BNS_VALUES_G, CM, id), \ 141 SRI(CM_BNS_VALUES_B, CM, id), \ 142 SRI(CM_MEM_PWR_CTRL, CM, id), \ 143 SRI(CM_RGAM_LUT_DATA, CM, id), \ 144 SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ 145 SRI(CM_RGAM_LUT_INDEX, CM, id), \ 146 SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ 147 SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ 148 SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ 149 SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ 150 SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ 151 SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ 152 SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ 153 SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ 154 SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ 155 SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ 156 SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ 157 SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ 158 SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ 159 SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ 160 SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ 161 SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ 162 SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ 163 SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ 164 SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ 165 SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ 166 SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ 167 SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ 168 SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ 169 SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ 170 SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ 171 SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ 172 SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ 173 SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ 174 SRI(CM_RGAM_CONTROL, CM, id), \ 175 SRI(CM_IGAM_CONTROL, CM, id), \ 176 SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ 177 SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ 178 SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ 179 SRI(CURSOR_CONTROL, CURSOR, id), \ 180 SRI(CM_CMOUT_CONTROL, CM, id) 181 182 183#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ 184 TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ 185 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\ 186 TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\ 187 TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\ 188 TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\ 189 TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\ 190 TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\ 191 TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\ 192 TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\ 193 TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\ 194 TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\ 195 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\ 196 TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\ 197 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ 198 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ 199 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ 200 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ 201 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ 202 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ 203 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ 204 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ 205 TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ 206 TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ 207 TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ 208 TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ 209 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ 210 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ 211 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ 212 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ 213 TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ 214 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ 215 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ 216 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ 217 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ 218 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ 219 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ 220 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ 221 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ 222 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ 223 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ 224 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ 225 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ 226 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ 227 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ 228 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ 229 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ 230 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ 231 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ 232 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ 233 TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ 234 TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ 235 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ 236 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ 237 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ 238 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ 239 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ 240 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ 241 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ 242 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ 243 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ 244 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ 245 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ 246 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ 247 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ 248 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ 249 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ 250 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ 251 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ 252 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ 253 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ 254 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ 255 TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ 256 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ 257 TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \ 258 TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \ 259 TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ 260 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ 261 TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ 262 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ 263 TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ 264 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ 265 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ 266 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ 267 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ 268 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ 269 TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ 270 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 271 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 272 TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 273 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ 274 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ 275 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ 276 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ 277 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ 278 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ 279 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ 280 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ 281 TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ 282 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ 283 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 284 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ 285 TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 286 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ 287 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 288 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ 289 TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 290 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ 291 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ 292 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ 293 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ 294 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ 295 TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ 296 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 297 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 298 TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 299 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ 300 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ 301 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ 302 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ 303 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ 304 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ 305 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ 306 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ 307 TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ 308 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ 309 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 310 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ 311 TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 312 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ 313 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ 314 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ 315 TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ 316 TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ 317 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ 318 TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ 319 TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ 320 TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ 321 TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ 322 TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ 323 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ 324 TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ 325 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ 326 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ 327 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ 328 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ 329 TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ 330 TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ 331 TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ 332 TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \ 333 TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \ 334 TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ 335 TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh) 336 337#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ 338 TF_REG_LIST_SH_MASK_DCN(mask_sh),\ 339 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\ 340 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\ 341 TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\ 342 TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\ 343 TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\ 344 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\ 345 TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\ 346 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\ 347 TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\ 348 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\ 349 TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\ 350 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\ 351 TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\ 352 TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ 353 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ 354 TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ 355 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ 356 TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ 357 TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ 358 TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ 359 TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ 360 TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \ 361 TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \ 362 TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \ 363 TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ 364 TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ 365 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ 366 TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ 367 TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ 368 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ 369 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ 370 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ 371 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ 372 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ 373 TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ 374 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 375 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 376 TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 377 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ 378 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ 379 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ 380 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ 381 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ 382 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ 383 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ 384 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ 385 TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ 386 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ 387 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 388 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ 389 TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 390 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ 391 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ 392 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ 393 TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ 394 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ 395 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ 396 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ 397 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ 398 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ 399 TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ 400 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ 401 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ 402 TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ 403 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ 404 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ 405 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ 406 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ 407 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ 408 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ 409 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ 410 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ 411 TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ 412 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ 413 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ 414 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ 415 TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ 416 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ 417 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ 418 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ 419 TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ 420 TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ 421 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ 422 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ 423 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ 424 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ 425 TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ 426 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ 427 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ 428 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ 429 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ 430 TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ 431 TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ 432 TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ 433 TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ 434 TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ 435 TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \ 436 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 437 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 438 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 439 TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 440 TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh) 441 442/* 443 * 444 DCN1 CM debug status register definition 445 446 register :ID9_CM_STATUS do 447 implement_ref :cm 448 map to: :cmdebugind, at: j 449 width 32 450 disclosure NEVER 451 452 field :ID9_VUPDATE_CFG, [0], R 453 field :ID9_IGAM_LUT_MODE, [2..1], R 454 field :ID9_BNS_BYPASS, [3], R 455 field :ID9_ICSC_MODE, [5..4], R 456 field :ID9_DGAM_LUT_MODE, [8..6], R 457 field :ID9_HDR_BYPASS, [9], R 458 field :ID9_GAMUT_REMAP_MODE, [11..10], R 459 field :ID9_RGAM_LUT_MODE, [14..12], R 460 #1 free bit 461 field :ID9_OCSC_MODE, [18..16], R 462 field :ID9_DENORM_MODE, [21..19], R 463 field :ID9_ROUND_TRUNC_MODE, [25..22], R 464 field :ID9_DITHER_EN, [26], R 465 field :ID9_DITHER_MODE, [28..27], R 466 end 467*/ 468 469#define TF_DEBUG_REG_LIST_SH_DCN10 \ 470 .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \ 471 .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16 472 473#define TF_DEBUG_REG_LIST_MASK_DCN10 \ 474 .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \ 475 .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000 476 477#define TF_REG_FIELD_LIST(type) \ 478 type EXT_OVERSCAN_LEFT; \ 479 type EXT_OVERSCAN_RIGHT; \ 480 type EXT_OVERSCAN_BOTTOM; \ 481 type EXT_OVERSCAN_TOP; \ 482 type OTG_H_BLANK_START; \ 483 type OTG_H_BLANK_END; \ 484 type OTG_V_BLANK_START; \ 485 type OTG_V_BLANK_END; \ 486 type PIXEL_DEPTH; \ 487 type PIXEL_EXPAN_MODE; \ 488 type PIXEL_REDUCE_MODE; \ 489 type DYNAMIC_PIXEL_DEPTH; \ 490 type DITHER_EN; \ 491 type INTERLEAVE_EN; \ 492 type LB_DATA_FORMAT__ALPHA_EN; \ 493 type MEMORY_CONFIG; \ 494 type LB_MAX_PARTITIONS; \ 495 type AUTOCAL_MODE; \ 496 type AUTOCAL_NUM_PIPE; \ 497 type AUTOCAL_PIPE_ID; \ 498 type SCL_BLACK_OFFSET_RGB_Y; \ 499 type SCL_BLACK_OFFSET_CBCR; \ 500 type SCL_V_NUM_TAPS; \ 501 type SCL_H_NUM_TAPS; \ 502 type SCL_V_NUM_TAPS_C; \ 503 type SCL_H_NUM_TAPS_C; \ 504 type SCL_COEF_RAM_TAP_PAIR_IDX; \ 505 type SCL_COEF_RAM_PHASE; \ 506 type SCL_COEF_RAM_FILTER_TYPE; \ 507 type SCL_COEF_RAM_EVEN_TAP_COEF; \ 508 type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \ 509 type SCL_COEF_RAM_ODD_TAP_COEF; \ 510 type SCL_COEF_RAM_ODD_TAP_COEF_EN; \ 511 type SCL_H_2TAP_HARDCODE_COEF_EN; \ 512 type SCL_H_2TAP_SHARP_EN; \ 513 type SCL_H_2TAP_SHARP_FACTOR; \ 514 type SCL_V_2TAP_HARDCODE_COEF_EN; \ 515 type SCL_V_2TAP_SHARP_EN; \ 516 type SCL_V_2TAP_SHARP_FACTOR; \ 517 type SCL_COEF_RAM_SELECT; \ 518 type DSCL_MODE; \ 519 type RECOUT_START_X; \ 520 type RECOUT_START_Y; \ 521 type RECOUT_WIDTH; \ 522 type RECOUT_HEIGHT; \ 523 type MPC_WIDTH; \ 524 type MPC_HEIGHT; \ 525 type SCL_H_SCALE_RATIO; \ 526 type SCL_V_SCALE_RATIO; \ 527 type SCL_H_SCALE_RATIO_C; \ 528 type SCL_V_SCALE_RATIO_C; \ 529 type SCL_H_INIT_FRAC; \ 530 type SCL_H_INIT_INT; \ 531 type SCL_H_INIT_FRAC_C; \ 532 type SCL_H_INIT_INT_C; \ 533 type SCL_V_INIT_FRAC; \ 534 type SCL_V_INIT_INT; \ 535 type SCL_V_INIT_FRAC_BOT; \ 536 type SCL_V_INIT_INT_BOT; \ 537 type SCL_V_INIT_FRAC_C; \ 538 type SCL_V_INIT_INT_C; \ 539 type SCL_V_INIT_FRAC_BOT_C; \ 540 type SCL_V_INIT_INT_BOT_C; \ 541 type SCL_CHROMA_COEF_MODE; \ 542 type SCL_COEF_RAM_SELECT_CURRENT; \ 543 type LUT_MEM_PWR_FORCE; \ 544 type LUT_MEM_PWR_STATE; \ 545 type CM_GAMUT_REMAP_MODE; \ 546 type CM_GAMUT_REMAP_C11; \ 547 type CM_GAMUT_REMAP_C12; \ 548 type CM_GAMUT_REMAP_C13; \ 549 type CM_GAMUT_REMAP_C14; \ 550 type CM_GAMUT_REMAP_C21; \ 551 type CM_GAMUT_REMAP_C22; \ 552 type CM_GAMUT_REMAP_C23; \ 553 type CM_GAMUT_REMAP_C24; \ 554 type CM_GAMUT_REMAP_C31; \ 555 type CM_GAMUT_REMAP_C32; \ 556 type CM_GAMUT_REMAP_C33; \ 557 type CM_GAMUT_REMAP_C34; \ 558 type CM_COMA_C11; \ 559 type CM_COMA_C12; \ 560 type CM_COMA_C33; \ 561 type CM_COMA_C34; \ 562 type CM_COMB_C11; \ 563 type CM_COMB_C12; \ 564 type CM_COMB_C33; \ 565 type CM_COMB_C34; \ 566 type CM_OCSC_MODE; \ 567 type CM_OCSC_C11; \ 568 type CM_OCSC_C12; \ 569 type CM_OCSC_C33; \ 570 type CM_OCSC_C34; \ 571 type RGAM_MEM_PWR_FORCE; \ 572 type CM_RGAM_LUT_DATA; \ 573 type CM_RGAM_LUT_WRITE_EN_MASK; \ 574 type CM_RGAM_LUT_WRITE_SEL; \ 575 type CM_RGAM_LUT_INDEX; \ 576 type CM_RGAM_RAMB_EXP_REGION_START_B; \ 577 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 578 type CM_RGAM_RAMB_EXP_REGION_START_G; \ 579 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 580 type CM_RGAM_RAMB_EXP_REGION_START_R; \ 581 type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 582 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 583 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 584 type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 585 type CM_RGAM_RAMB_EXP_REGION_END_B; \ 586 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 587 type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \ 588 type CM_RGAM_RAMB_EXP_REGION_END_G; \ 589 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 590 type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \ 591 type CM_RGAM_RAMB_EXP_REGION_END_R; \ 592 type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 593 type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \ 594 type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 595 type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 596 type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 597 type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 598 type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ 599 type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 600 type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ 601 type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 602 type CM_RGAM_RAMA_EXP_REGION_START_B; \ 603 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 604 type CM_RGAM_RAMA_EXP_REGION_START_G; \ 605 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 606 type CM_RGAM_RAMA_EXP_REGION_START_R; \ 607 type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 608 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 609 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 610 type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 611 type CM_RGAM_RAMA_EXP_REGION_END_B; \ 612 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 613 type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \ 614 type CM_RGAM_RAMA_EXP_REGION_END_G; \ 615 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 616 type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \ 617 type CM_RGAM_RAMA_EXP_REGION_END_R; \ 618 type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 619 type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \ 620 type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 621 type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 622 type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 623 type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 624 type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ 625 type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 626 type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ 627 type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 628 type CM_RGAM_LUT_MODE; \ 629 type CM_CMOUT_ROUND_TRUNC_MODE; \ 630 type CM_BLNDGAM_LUT_MODE; \ 631 type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \ 632 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 633 type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \ 634 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 635 type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \ 636 type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 637 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 638 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 639 type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 640 type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \ 641 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 642 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \ 643 type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \ 644 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 645 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \ 646 type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \ 647 type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 648 type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \ 649 type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 650 type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 651 type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 652 type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 653 type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ 654 type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ 655 type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ 656 type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ 657 type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ 658 type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ 659 type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ 660 type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ 661 type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ 662 type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ 663 type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ 664 type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ 665 type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ 666 type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ 667 type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ 668 type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ 669 type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ 670 type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ 671 type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ 672 type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ 673 type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ 674 type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ 675 type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ 676 type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ 677 type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ 678 type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 679 type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ 680 type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 681 type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \ 682 type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \ 683 type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \ 684 type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \ 685 type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \ 686 type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \ 687 type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \ 688 type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \ 689 type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \ 690 type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \ 691 type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \ 692 type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \ 693 type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \ 694 type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \ 695 type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \ 696 type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \ 697 type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \ 698 type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \ 699 type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \ 700 type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \ 701 type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \ 702 type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \ 703 type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \ 704 type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \ 705 type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \ 706 type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \ 707 type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \ 708 type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \ 709 type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \ 710 type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \ 711 type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \ 712 type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \ 713 type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ 714 type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 715 type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ 716 type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 717 type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \ 718 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 719 type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \ 720 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 721 type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \ 722 type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 723 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 724 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 725 type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 726 type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \ 727 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 728 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \ 729 type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \ 730 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 731 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \ 732 type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \ 733 type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 734 type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \ 735 type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 736 type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 737 type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 738 type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 739 type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ 740 type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 741 type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ 742 type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 743 type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ 744 type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 745 type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ 746 type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 747 type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ 748 type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 749 type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ 750 type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 751 type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ 752 type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 753 type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ 754 type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 755 type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ 756 type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 757 type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ 758 type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 759 type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ 760 type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 761 type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ 762 type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 763 type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 764 type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 765 type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 766 type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 767 type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ 768 type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 769 type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ 770 type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 771 type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ 772 type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 773 type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ 774 type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 775 type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ 776 type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 777 type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ 778 type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 779 type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ 780 type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 781 type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ 782 type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 783 type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ 784 type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 785 type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ 786 type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 787 type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ 788 type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 789 type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ 790 type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 791 type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ 792 type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 793 type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ 794 type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 795 type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ 796 type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 797 type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ 798 type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 799 type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ 800 type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 801 type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ 802 type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 803 type CM_BLNDGAM_LUT_WRITE_EN_MASK; \ 804 type CM_BLNDGAM_LUT_WRITE_SEL; \ 805 type CM_BLNDGAM_CONFIG_STATUS; \ 806 type CM_BLNDGAM_LUT_INDEX; \ 807 type BLNDGAM_MEM_PWR_FORCE; \ 808 type CM_3DLUT_MODE; \ 809 type CM_3DLUT_SIZE; \ 810 type CM_3DLUT_INDEX; \ 811 type CM_3DLUT_DATA0; \ 812 type CM_3DLUT_DATA1; \ 813 type CM_3DLUT_DATA_30BIT; \ 814 type CM_3DLUT_WRITE_EN_MASK; \ 815 type CM_3DLUT_RAM_SEL; \ 816 type CM_3DLUT_30BIT_EN; \ 817 type CM_3DLUT_CONFIG_STATUS; \ 818 type CM_3DLUT_READ_SEL; \ 819 type CM_SHAPER_LUT_MODE; \ 820 type CM_SHAPER_RAMB_EXP_REGION_START_B; \ 821 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \ 822 type CM_SHAPER_RAMB_EXP_REGION_START_G; \ 823 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \ 824 type CM_SHAPER_RAMB_EXP_REGION_START_R; \ 825 type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \ 826 type CM_SHAPER_RAMB_EXP_REGION_END_B; \ 827 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \ 828 type CM_SHAPER_RAMB_EXP_REGION_END_G; \ 829 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \ 830 type CM_SHAPER_RAMB_EXP_REGION_END_R; \ 831 type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \ 832 type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \ 833 type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 834 type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \ 835 type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 836 type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \ 837 type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \ 838 type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \ 839 type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \ 840 type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \ 841 type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \ 842 type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \ 843 type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \ 844 type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \ 845 type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \ 846 type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \ 847 type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \ 848 type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \ 849 type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \ 850 type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \ 851 type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \ 852 type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \ 853 type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \ 854 type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \ 855 type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \ 856 type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \ 857 type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \ 858 type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \ 859 type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \ 860 type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \ 861 type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 862 type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \ 863 type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 864 type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \ 865 type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \ 866 type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \ 867 type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \ 868 type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \ 869 type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \ 870 type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \ 871 type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \ 872 type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \ 873 type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \ 874 type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \ 875 type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \ 876 type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \ 877 type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \ 878 type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \ 879 type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \ 880 type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \ 881 type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \ 882 type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \ 883 type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \ 884 type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \ 885 type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \ 886 type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \ 887 type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \ 888 type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \ 889 type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \ 890 type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \ 891 type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \ 892 type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \ 893 type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \ 894 type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \ 895 type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \ 896 type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \ 897 type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \ 898 type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \ 899 type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \ 900 type CM_SHAPER_RAMA_EXP_REGION_START_B; \ 901 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ 902 type CM_SHAPER_RAMA_EXP_REGION_START_G; \ 903 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \ 904 type CM_SHAPER_RAMA_EXP_REGION_START_R; \ 905 type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \ 906 type CM_SHAPER_RAMA_EXP_REGION_END_B; \ 907 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \ 908 type CM_SHAPER_RAMA_EXP_REGION_END_G; \ 909 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \ 910 type CM_SHAPER_RAMA_EXP_REGION_END_R; \ 911 type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \ 912 type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \ 913 type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 914 type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ 915 type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 916 type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ 917 type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 918 type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \ 919 type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 920 type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \ 921 type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 922 type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \ 923 type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 924 type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ 925 type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 926 type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ 927 type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 928 type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \ 929 type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 930 type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \ 931 type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 932 type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \ 933 type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 934 type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ 935 type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 936 type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ 937 type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 938 type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \ 939 type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 940 type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \ 941 type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 942 type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \ 943 type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 944 type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ 945 type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 946 type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ 947 type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 948 type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \ 949 type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 950 type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \ 951 type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 952 type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \ 953 type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 954 type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ 955 type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 956 type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ 957 type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 958 type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \ 959 type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 960 type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \ 961 type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 962 type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \ 963 type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 964 type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ 965 type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 966 type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ 967 type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 968 type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \ 969 type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 970 type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \ 971 type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 972 type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \ 973 type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 974 type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ 975 type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 976 type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ 977 type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 978 type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \ 979 type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 980 type CM_SHAPER_LUT_WRITE_EN_MASK; \ 981 type CM_SHAPER_CONFIG_STATUS; \ 982 type CM_SHAPER_LUT_WRITE_SEL; \ 983 type CM_SHAPER_LUT_INDEX; \ 984 type CM_SHAPER_LUT_DATA; \ 985 type CM_DGAM_CONFIG_STATUS; \ 986 type CM_ICSC_MODE; \ 987 type CM_ICSC_C11; \ 988 type CM_ICSC_C12; \ 989 type CM_ICSC_C33; \ 990 type CM_ICSC_C34; \ 991 type CM_BNS_BIAS_R; \ 992 type CM_BNS_BIAS_G; \ 993 type CM_BNS_BIAS_B; \ 994 type CM_BNS_SCALE_R; \ 995 type CM_BNS_SCALE_G; \ 996 type CM_BNS_SCALE_B; \ 997 type CM_DGAM_RAMB_EXP_REGION_START_B; \ 998 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ 999 type CM_DGAM_RAMB_EXP_REGION_START_G; \ 1000 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ 1001 type CM_DGAM_RAMB_EXP_REGION_START_R; \ 1002 type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ 1003 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ 1004 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ 1005 type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ 1006 type CM_DGAM_RAMB_EXP_REGION_END_B; \ 1007 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \ 1008 type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \ 1009 type CM_DGAM_RAMB_EXP_REGION_END_G; \ 1010 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \ 1011 type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \ 1012 type CM_DGAM_RAMB_EXP_REGION_END_R; \ 1013 type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \ 1014 type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \ 1015 type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ 1016 type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ 1017 type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ 1018 type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ 1019 type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ 1020 type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ 1021 type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ 1022 type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ 1023 type CM_DGAM_RAMA_EXP_REGION_START_B; \ 1024 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 1025 type CM_DGAM_RAMA_EXP_REGION_START_G; \ 1026 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 1027 type CM_DGAM_RAMA_EXP_REGION_START_R; \ 1028 type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 1029 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ 1030 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ 1031 type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ 1032 type CM_DGAM_RAMA_EXP_REGION_END_B; \ 1033 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 1034 type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \ 1035 type CM_DGAM_RAMA_EXP_REGION_END_G; \ 1036 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 1037 type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \ 1038 type CM_DGAM_RAMA_EXP_REGION_END_R; \ 1039 type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 1040 type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \ 1041 type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 1042 type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 1043 type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 1044 type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 1045 type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 1046 type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 1047 type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 1048 type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 1049 type SHARED_MEM_PWR_DIS; \ 1050 type CM_IGAM_LUT_FORMAT_R; \ 1051 type CM_IGAM_LUT_FORMAT_G; \ 1052 type CM_IGAM_LUT_FORMAT_B; \ 1053 type CM_IGAM_LUT_HOST_EN; \ 1054 type CM_IGAM_LUT_RW_MODE; \ 1055 type CM_IGAM_LUT_WRITE_EN_MASK; \ 1056 type CM_IGAM_LUT_SEL; \ 1057 type CM_IGAM_LUT_SEQ_COLOR; \ 1058 type CM_IGAM_DGAM_CONFIG_STATUS; \ 1059 type CM_DGAM_LUT_WRITE_EN_MASK; \ 1060 type CM_DGAM_LUT_WRITE_SEL; \ 1061 type CM_DGAM_LUT_INDEX; \ 1062 type CM_DGAM_LUT_DATA; \ 1063 type CM_DGAM_LUT_MODE; \ 1064 type CM_IGAM_LUT_MODE; \ 1065 type CM_IGAM_INPUT_FORMAT; \ 1066 type CM_IGAM_LUT_RW_INDEX; \ 1067 type CM_BYPASS_EN; \ 1068 type FORMAT_EXPANSION_MODE; \ 1069 type CNVC_BYPASS; \ 1070 type OUTPUT_FP; \ 1071 type CNVC_SURFACE_PIXEL_FORMAT; \ 1072 type CURSOR_MODE; \ 1073 type CURSOR_PITCH; \ 1074 type CURSOR_LINES_PER_CHUNK; \ 1075 type CURSOR_ENABLE; \ 1076 type CUR0_MODE; \ 1077 type CUR0_EXPANSION_MODE; \ 1078 type CUR0_ENABLE; \ 1079 type CM_BYPASS; \ 1080 type CM_TEST_DEBUG_INDEX; \ 1081 type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \ 1082 type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\ 1083 type FORMAT_CONTROL__ALPHA_EN; \ 1084 type CUR0_COLOR0; \ 1085 type CUR0_COLOR1; \ 1086 type DPPCLK_RATE_CONTROL; \ 1087 type DPP_CLOCK_ENABLE; \ 1088 type CM_HDR_MULT_COEF; \ 1089 type CUR0_FP_BIAS; \ 1090 type CUR0_FP_SCALE; 1091 1092struct dcn_dpp_shift { 1093 TF_REG_FIELD_LIST(uint8_t) 1094}; 1095 1096struct dcn_dpp_mask { 1097 TF_REG_FIELD_LIST(uint32_t) 1098}; 1099 1100#define DPP_COMMON_REG_VARIABLE_LIST \ 1101 uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \ 1102 uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \ 1103 uint32_t OTG_H_BLANK; \ 1104 uint32_t OTG_V_BLANK; \ 1105 uint32_t DSCL_MEM_PWR_CTRL; \ 1106 uint32_t DSCL_MEM_PWR_STATUS; \ 1107 uint32_t SCL_MODE; \ 1108 uint32_t LB_DATA_FORMAT; \ 1109 uint32_t LB_MEMORY_CTRL; \ 1110 uint32_t DSCL_AUTOCAL; \ 1111 uint32_t SCL_BLACK_OFFSET; \ 1112 uint32_t SCL_TAP_CONTROL; \ 1113 uint32_t SCL_COEF_RAM_TAP_SELECT; \ 1114 uint32_t SCL_COEF_RAM_TAP_DATA; \ 1115 uint32_t DSCL_2TAP_CONTROL; \ 1116 uint32_t MPC_SIZE; \ 1117 uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \ 1118 uint32_t SCL_VERT_FILTER_SCALE_RATIO; \ 1119 uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \ 1120 uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \ 1121 uint32_t SCL_HORZ_FILTER_INIT; \ 1122 uint32_t SCL_HORZ_FILTER_INIT_C; \ 1123 uint32_t SCL_VERT_FILTER_INIT; \ 1124 uint32_t SCL_VERT_FILTER_INIT_BOT; \ 1125 uint32_t SCL_VERT_FILTER_INIT_C; \ 1126 uint32_t SCL_VERT_FILTER_INIT_BOT_C; \ 1127 uint32_t RECOUT_START; \ 1128 uint32_t RECOUT_SIZE; \ 1129 uint32_t CM_GAMUT_REMAP_CONTROL; \ 1130 uint32_t CM_GAMUT_REMAP_C11_C12; \ 1131 uint32_t CM_GAMUT_REMAP_C13_C14; \ 1132 uint32_t CM_GAMUT_REMAP_C21_C22; \ 1133 uint32_t CM_GAMUT_REMAP_C23_C24; \ 1134 uint32_t CM_GAMUT_REMAP_C31_C32; \ 1135 uint32_t CM_GAMUT_REMAP_C33_C34; \ 1136 uint32_t CM_COMA_C11_C12; \ 1137 uint32_t CM_COMA_C33_C34; \ 1138 uint32_t CM_COMB_C11_C12; \ 1139 uint32_t CM_COMB_C33_C34; \ 1140 uint32_t CM_OCSC_CONTROL; \ 1141 uint32_t CM_OCSC_C11_C12; \ 1142 uint32_t CM_OCSC_C33_C34; \ 1143 uint32_t CM_MEM_PWR_CTRL; \ 1144 uint32_t CM_RGAM_LUT_DATA; \ 1145 uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \ 1146 uint32_t CM_RGAM_LUT_INDEX; \ 1147 uint32_t CM_RGAM_RAMB_START_CNTL_B; \ 1148 uint32_t CM_RGAM_RAMB_START_CNTL_G; \ 1149 uint32_t CM_RGAM_RAMB_START_CNTL_R; \ 1150 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \ 1151 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \ 1152 uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \ 1153 uint32_t CM_RGAM_RAMB_END_CNTL1_B; \ 1154 uint32_t CM_RGAM_RAMB_END_CNTL2_B; \ 1155 uint32_t CM_RGAM_RAMB_END_CNTL1_G; \ 1156 uint32_t CM_RGAM_RAMB_END_CNTL2_G; \ 1157 uint32_t CM_RGAM_RAMB_END_CNTL1_R; \ 1158 uint32_t CM_RGAM_RAMB_END_CNTL2_R; \ 1159 uint32_t CM_RGAM_RAMB_REGION_0_1; \ 1160 uint32_t CM_RGAM_RAMB_REGION_32_33; \ 1161 uint32_t CM_RGAM_RAMA_START_CNTL_B; \ 1162 uint32_t CM_RGAM_RAMA_START_CNTL_G; \ 1163 uint32_t CM_RGAM_RAMA_START_CNTL_R; \ 1164 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \ 1165 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \ 1166 uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \ 1167 uint32_t CM_RGAM_RAMA_END_CNTL1_B; \ 1168 uint32_t CM_RGAM_RAMA_END_CNTL2_B; \ 1169 uint32_t CM_RGAM_RAMA_END_CNTL1_G; \ 1170 uint32_t CM_RGAM_RAMA_END_CNTL2_G; \ 1171 uint32_t CM_RGAM_RAMA_END_CNTL1_R; \ 1172 uint32_t CM_RGAM_RAMA_END_CNTL2_R; \ 1173 uint32_t CM_RGAM_RAMA_REGION_0_1; \ 1174 uint32_t CM_RGAM_RAMA_REGION_32_33; \ 1175 uint32_t CM_RGAM_CONTROL; \ 1176 uint32_t CM_CMOUT_CONTROL; \ 1177 uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \ 1178 uint32_t CM_BLNDGAM_CONTROL; \ 1179 uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \ 1180 uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \ 1181 uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \ 1182 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \ 1183 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \ 1184 uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \ 1185 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \ 1186 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \ 1187 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \ 1188 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \ 1189 uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \ 1190 uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \ 1191 uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \ 1192 uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \ 1193 uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \ 1194 uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \ 1195 uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \ 1196 uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \ 1197 uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \ 1198 uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \ 1199 uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \ 1200 uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \ 1201 uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \ 1202 uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \ 1203 uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \ 1204 uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \ 1205 uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \ 1206 uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \ 1207 uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \ 1208 uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \ 1209 uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \ 1210 uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \ 1211 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \ 1212 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \ 1213 uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \ 1214 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \ 1215 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \ 1216 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \ 1217 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \ 1218 uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \ 1219 uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \ 1220 uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \ 1221 uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \ 1222 uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \ 1223 uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \ 1224 uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \ 1225 uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \ 1226 uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \ 1227 uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \ 1228 uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \ 1229 uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \ 1230 uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \ 1231 uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \ 1232 uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \ 1233 uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \ 1234 uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \ 1235 uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \ 1236 uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \ 1237 uint32_t CM_BLNDGAM_LUT_INDEX; \ 1238 uint32_t CM_3DLUT_MODE; \ 1239 uint32_t CM_3DLUT_INDEX; \ 1240 uint32_t CM_3DLUT_DATA; \ 1241 uint32_t CM_3DLUT_DATA_30BIT; \ 1242 uint32_t CM_3DLUT_READ_WRITE_CONTROL; \ 1243 uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \ 1244 uint32_t CM_SHAPER_CONTROL; \ 1245 uint32_t CM_SHAPER_RAMB_START_CNTL_B; \ 1246 uint32_t CM_SHAPER_RAMB_START_CNTL_G; \ 1247 uint32_t CM_SHAPER_RAMB_START_CNTL_R; \ 1248 uint32_t CM_SHAPER_RAMB_END_CNTL_B; \ 1249 uint32_t CM_SHAPER_RAMB_END_CNTL_G; \ 1250 uint32_t CM_SHAPER_RAMB_END_CNTL_R; \ 1251 uint32_t CM_SHAPER_RAMB_REGION_0_1; \ 1252 uint32_t CM_SHAPER_RAMB_REGION_2_3; \ 1253 uint32_t CM_SHAPER_RAMB_REGION_4_5; \ 1254 uint32_t CM_SHAPER_RAMB_REGION_6_7; \ 1255 uint32_t CM_SHAPER_RAMB_REGION_8_9; \ 1256 uint32_t CM_SHAPER_RAMB_REGION_10_11; \ 1257 uint32_t CM_SHAPER_RAMB_REGION_12_13; \ 1258 uint32_t CM_SHAPER_RAMB_REGION_14_15; \ 1259 uint32_t CM_SHAPER_RAMB_REGION_16_17; \ 1260 uint32_t CM_SHAPER_RAMB_REGION_18_19; \ 1261 uint32_t CM_SHAPER_RAMB_REGION_20_21; \ 1262 uint32_t CM_SHAPER_RAMB_REGION_22_23; \ 1263 uint32_t CM_SHAPER_RAMB_REGION_24_25; \ 1264 uint32_t CM_SHAPER_RAMB_REGION_26_27; \ 1265 uint32_t CM_SHAPER_RAMB_REGION_28_29; \ 1266 uint32_t CM_SHAPER_RAMB_REGION_30_31; \ 1267 uint32_t CM_SHAPER_RAMB_REGION_32_33; \ 1268 uint32_t CM_SHAPER_RAMA_START_CNTL_B; \ 1269 uint32_t CM_SHAPER_RAMA_START_CNTL_G; \ 1270 uint32_t CM_SHAPER_RAMA_START_CNTL_R; \ 1271 uint32_t CM_SHAPER_RAMA_END_CNTL_B; \ 1272 uint32_t CM_SHAPER_RAMA_END_CNTL_G; \ 1273 uint32_t CM_SHAPER_RAMA_END_CNTL_R; \ 1274 uint32_t CM_SHAPER_RAMA_REGION_0_1; \ 1275 uint32_t CM_SHAPER_RAMA_REGION_2_3; \ 1276 uint32_t CM_SHAPER_RAMA_REGION_4_5; \ 1277 uint32_t CM_SHAPER_RAMA_REGION_6_7; \ 1278 uint32_t CM_SHAPER_RAMA_REGION_8_9; \ 1279 uint32_t CM_SHAPER_RAMA_REGION_10_11; \ 1280 uint32_t CM_SHAPER_RAMA_REGION_12_13; \ 1281 uint32_t CM_SHAPER_RAMA_REGION_14_15; \ 1282 uint32_t CM_SHAPER_RAMA_REGION_16_17; \ 1283 uint32_t CM_SHAPER_RAMA_REGION_18_19; \ 1284 uint32_t CM_SHAPER_RAMA_REGION_20_21; \ 1285 uint32_t CM_SHAPER_RAMA_REGION_22_23; \ 1286 uint32_t CM_SHAPER_RAMA_REGION_24_25; \ 1287 uint32_t CM_SHAPER_RAMA_REGION_26_27; \ 1288 uint32_t CM_SHAPER_RAMA_REGION_28_29; \ 1289 uint32_t CM_SHAPER_RAMA_REGION_30_31; \ 1290 uint32_t CM_SHAPER_RAMA_REGION_32_33; \ 1291 uint32_t CM_SHAPER_LUT_INDEX; \ 1292 uint32_t CM_SHAPER_LUT_DATA; \ 1293 uint32_t CM_ICSC_CONTROL; \ 1294 uint32_t CM_ICSC_C11_C12; \ 1295 uint32_t CM_ICSC_C33_C34; \ 1296 uint32_t CM_BNS_VALUES_R; \ 1297 uint32_t CM_BNS_VALUES_G; \ 1298 uint32_t CM_BNS_VALUES_B; \ 1299 uint32_t CM_DGAM_RAMB_START_CNTL_B; \ 1300 uint32_t CM_DGAM_RAMB_START_CNTL_G; \ 1301 uint32_t CM_DGAM_RAMB_START_CNTL_R; \ 1302 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \ 1303 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \ 1304 uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \ 1305 uint32_t CM_DGAM_RAMB_END_CNTL1_B; \ 1306 uint32_t CM_DGAM_RAMB_END_CNTL2_B; \ 1307 uint32_t CM_DGAM_RAMB_END_CNTL1_G; \ 1308 uint32_t CM_DGAM_RAMB_END_CNTL2_G; \ 1309 uint32_t CM_DGAM_RAMB_END_CNTL1_R; \ 1310 uint32_t CM_DGAM_RAMB_END_CNTL2_R; \ 1311 uint32_t CM_DGAM_RAMB_REGION_0_1; \ 1312 uint32_t CM_DGAM_RAMB_REGION_14_15; \ 1313 uint32_t CM_DGAM_RAMA_START_CNTL_B; \ 1314 uint32_t CM_DGAM_RAMA_START_CNTL_G; \ 1315 uint32_t CM_DGAM_RAMA_START_CNTL_R; \ 1316 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \ 1317 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \ 1318 uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \ 1319 uint32_t CM_DGAM_RAMA_END_CNTL1_B; \ 1320 uint32_t CM_DGAM_RAMA_END_CNTL2_B; \ 1321 uint32_t CM_DGAM_RAMA_END_CNTL1_G; \ 1322 uint32_t CM_DGAM_RAMA_END_CNTL2_G; \ 1323 uint32_t CM_DGAM_RAMA_END_CNTL1_R; \ 1324 uint32_t CM_DGAM_RAMA_END_CNTL2_R; \ 1325 uint32_t CM_DGAM_RAMA_REGION_0_1; \ 1326 uint32_t CM_DGAM_RAMA_REGION_14_15; \ 1327 uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \ 1328 uint32_t CM_DGAM_LUT_INDEX; \ 1329 uint32_t CM_DGAM_LUT_DATA; \ 1330 uint32_t CM_CONTROL; \ 1331 uint32_t CM_DGAM_CONTROL; \ 1332 uint32_t CM_IGAM_CONTROL; \ 1333 uint32_t CM_IGAM_LUT_RW_CONTROL; \ 1334 uint32_t CM_IGAM_LUT_RW_INDEX; \ 1335 uint32_t CM_IGAM_LUT_SEQ_COLOR; \ 1336 uint32_t CM_TEST_DEBUG_INDEX; \ 1337 uint32_t CM_TEST_DEBUG_DATA; \ 1338 uint32_t FORMAT_CONTROL; \ 1339 uint32_t CNVC_SURFACE_PIXEL_FORMAT; \ 1340 uint32_t CURSOR_CONTROL; \ 1341 uint32_t CURSOR0_CONTROL; \ 1342 uint32_t CURSOR0_COLOR0; \ 1343 uint32_t CURSOR0_COLOR1; \ 1344 uint32_t DPP_CONTROL; \ 1345 uint32_t CM_HDR_MULT_COEF; \ 1346 uint32_t CURSOR0_FP_SCALE_BIAS; 1347 1348struct dcn_dpp_registers { 1349 DPP_COMMON_REG_VARIABLE_LIST 1350}; 1351 1352struct dcn10_dpp { 1353 struct dpp base; 1354 1355 const struct dcn_dpp_registers *tf_regs; 1356 const struct dcn_dpp_shift *tf_shift; 1357 const struct dcn_dpp_mask *tf_mask; 1358 1359 const uint16_t *filter_v; 1360 const uint16_t *filter_h; 1361 const uint16_t *filter_v_c; 1362 const uint16_t *filter_h_c; 1363 int lb_pixel_depth_supported; 1364 int lb_memory_size; 1365 int lb_bits_per_entry; 1366 bool is_write_to_ram_a_safe; 1367 struct scaler_data scl_data; 1368 struct pwl_params pwl_data; 1369}; 1370 1371enum dcn10_input_csc_select { 1372 INPUT_CSC_SELECT_BYPASS = 0, 1373 INPUT_CSC_SELECT_ICSC = 1, 1374 INPUT_CSC_SELECT_COMA = 2 1375}; 1376 1377void dpp1_set_cursor_attributes( 1378 struct dpp *dpp_base, 1379 struct dc_cursor_attributes *cursor_attributes); 1380 1381void dpp1_set_cursor_position( 1382 struct dpp *dpp_base, 1383 const struct dc_cursor_position *pos, 1384 const struct dc_cursor_mi_param *param, 1385 uint32_t width, 1386 uint32_t height); 1387 1388void dpp1_cnv_set_optional_cursor_attributes( 1389 struct dpp *dpp_base, 1390 struct dpp_cursor_attributes *attr); 1391 1392bool dpp1_dscl_is_lb_conf_valid( 1393 int ceil_vratio, 1394 int num_partitions, 1395 int vtaps); 1396 1397void dpp1_dscl_calc_lb_num_partitions( 1398 const struct scaler_data *scl_data, 1399 enum lb_memory_config lb_config, 1400 int *num_part_y, 1401 int *num_part_c); 1402 1403void dpp1_degamma_ram_select( 1404 struct dpp *dpp_base, 1405 bool use_ram_a); 1406 1407void dpp1_program_degamma_luta_settings( 1408 struct dpp *dpp_base, 1409 const struct pwl_params *params); 1410 1411void dpp1_program_degamma_lutb_settings( 1412 struct dpp *dpp_base, 1413 const struct pwl_params *params); 1414 1415void dpp1_program_degamma_lut( 1416 struct dpp *dpp_base, 1417 const struct pwl_result_data *rgb, 1418 uint32_t num, 1419 bool is_ram_a); 1420 1421void dpp1_power_on_degamma_lut( 1422 struct dpp *dpp_base, 1423 bool power_on); 1424 1425void dpp1_program_input_csc( 1426 struct dpp *dpp_base, 1427 enum dc_color_space color_space, 1428 enum dcn10_input_csc_select select, 1429 const struct out_csc_color_matrix *tbl_entry); 1430 1431void dpp1_program_bias_and_scale( 1432 struct dpp *dpp_base, 1433 struct dc_bias_and_scale *params); 1434 1435void dpp1_program_input_lut( 1436 struct dpp *dpp_base, 1437 const struct dc_gamma *gamma); 1438 1439void dpp1_full_bypass(struct dpp *dpp_base); 1440 1441void dpp1_set_degamma( 1442 struct dpp *dpp_base, 1443 enum ipp_degamma_mode mode); 1444 1445void dpp1_set_degamma_pwl(struct dpp *dpp_base, 1446 const struct pwl_params *params); 1447 1448 1449void dpp_read_state(struct dpp *dpp_base, 1450 struct dcn_dpp_state *s); 1451 1452void dpp_reset(struct dpp *dpp_base); 1453 1454void dpp1_cm_program_regamma_lut( 1455 struct dpp *dpp_base, 1456 const struct pwl_result_data *rgb, 1457 uint32_t num); 1458 1459void dpp1_cm_power_on_regamma_lut( 1460 struct dpp *dpp_base, 1461 bool power_on); 1462 1463void dpp1_cm_configure_regamma_lut( 1464 struct dpp *dpp_base, 1465 bool is_ram_a); 1466 1467/*program re gamma RAM A*/ 1468void dpp1_cm_program_regamma_luta_settings( 1469 struct dpp *dpp_base, 1470 const struct pwl_params *params); 1471 1472/*program re gamma RAM B*/ 1473void dpp1_cm_program_regamma_lutb_settings( 1474 struct dpp *dpp_base, 1475 const struct pwl_params *params); 1476void dpp1_cm_set_output_csc_adjustment( 1477 struct dpp *dpp_base, 1478 const uint16_t *regval); 1479 1480void dpp1_cm_set_output_csc_default( 1481 struct dpp *dpp_base, 1482 enum dc_color_space colorspace); 1483 1484void dpp1_cm_set_gamut_remap( 1485 struct dpp *dpp, 1486 const struct dpp_grph_csc_adjustment *adjust); 1487 1488void dpp1_dscl_set_scaler_manual_scale( 1489 struct dpp *dpp_base, 1490 const struct scaler_data *scl_data); 1491 1492void dpp1_cnv_setup ( 1493 struct dpp *dpp_base, 1494 enum surface_pixel_format format, 1495 enum expansion_mode mode, 1496 struct dc_csc_transform input_csc_color_matrix, 1497 enum dc_color_space input_color_space, 1498 struct cnv_alpha_2bit_lut *alpha_2bit_lut); 1499 1500void dpp1_dppclk_control( 1501 struct dpp *dpp_base, 1502 bool dppclk_div, 1503 bool enable); 1504 1505void dpp1_set_hdr_multiplier( 1506 struct dpp *dpp_base, 1507 uint32_t multiplier); 1508 1509bool dpp1_get_optimal_number_of_taps( 1510 struct dpp *dpp, 1511 struct scaler_data *scl_data, 1512 const struct scaling_taps *in_taps); 1513 1514void dpp1_construct(struct dcn10_dpp *dpp1, 1515 struct dc_context *ctx, 1516 uint32_t inst, 1517 const struct dcn_dpp_registers *tf_regs, 1518 const struct dcn_dpp_shift *tf_shift, 1519 const struct dcn_dpp_mask *tf_mask); 1520#endif