cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn10_hubbub.h (16733B)


      1/*
      2 * Copyright 2016 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#ifndef __DC_HUBBUB_DCN10_H__
     27#define __DC_HUBBUB_DCN10_H__
     28
     29#include "core_types.h"
     30#include "dchubbub.h"
     31
     32#define TO_DCN10_HUBBUB(hubbub)\
     33	container_of(hubbub, struct dcn10_hubbub, base)
     34
     35#define HUBBUB_REG_LIST_DCN_COMMON()\
     36	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
     37	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
     38	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
     39	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
     40	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
     41	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
     42	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
     43	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
     44	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
     45	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
     46	SR(DCHUBBUB_ARB_SAT_LEVEL),\
     47	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
     48	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
     49	SR(DCHUBBUB_TEST_DEBUG_INDEX), \
     50	SR(DCHUBBUB_TEST_DEBUG_DATA),\
     51	SR(DCHUBBUB_SOFT_RESET)
     52
     53#define HUBBUB_VM_REG_LIST() \
     54	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
     55	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
     56	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
     57	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)
     58
     59#define HUBBUB_SR_WATERMARK_REG_LIST()\
     60	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
     61	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
     62	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
     63	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
     64	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
     65	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
     66	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
     67	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
     68
     69#define HUBBUB_REG_LIST_DCN10(id)\
     70	HUBBUB_REG_LIST_DCN_COMMON(), \
     71	HUBBUB_VM_REG_LIST(), \
     72	HUBBUB_SR_WATERMARK_REG_LIST(), \
     73	SR(DCHUBBUB_SDPIF_FB_TOP),\
     74	SR(DCHUBBUB_SDPIF_FB_BASE),\
     75	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
     76	SR(DCHUBBUB_SDPIF_AGP_BASE),\
     77	SR(DCHUBBUB_SDPIF_AGP_BOT),\
     78	SR(DCHUBBUB_SDPIF_AGP_TOP)
     79
     80struct dcn_hubbub_registers {
     81	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
     82	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
     83	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
     84	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
     85	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
     86	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
     87	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
     88	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
     89	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
     90	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
     91	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
     92	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
     93	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
     94	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
     95	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
     96	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
     97	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
     98	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
     99	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
    100	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
    101	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
    102	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
    103	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
    104	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
    105	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
    106	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
    107	uint32_t DCHUBBUB_TEST_DEBUG_DATA;
    108	uint32_t DCHUBBUB_SDPIF_FB_TOP;
    109	uint32_t DCHUBBUB_SDPIF_FB_BASE;
    110	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
    111	uint32_t DCHUBBUB_SDPIF_AGP_BASE;
    112	uint32_t DCHUBBUB_SDPIF_AGP_BOT;
    113	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
    114	uint32_t DCHUBBUB_CRC_CTRL;
    115	uint32_t DCHUBBUB_SOFT_RESET;
    116	uint32_t DCN_VM_FB_LOCATION_BASE;
    117	uint32_t DCN_VM_FB_LOCATION_TOP;
    118	uint32_t DCN_VM_FB_OFFSET;
    119	uint32_t DCN_VM_AGP_BOT;
    120	uint32_t DCN_VM_AGP_TOP;
    121	uint32_t DCN_VM_AGP_BASE;
    122	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
    123	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
    124	uint32_t DCN_VM_FAULT_ADDR_MSB;
    125	uint32_t DCN_VM_FAULT_ADDR_LSB;
    126	uint32_t DCN_VM_FAULT_CNTL;
    127	uint32_t DCN_VM_FAULT_STATUS;
    128	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
    129	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
    130	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
    131	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
    132	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
    133	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
    134	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
    135	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
    136	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
    137	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
    138	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
    139	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
    140	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
    141	uint32_t DCHVM_CTRL0;
    142	uint32_t DCHVM_MEM_CTRL;
    143	uint32_t DCHVM_CLK_CTRL;
    144	uint32_t DCHVM_RIOMMU_CTRL0;
    145	uint32_t DCHVM_RIOMMU_STAT0;
    146	uint32_t DCHUBBUB_DET0_CTRL;
    147	uint32_t DCHUBBUB_DET1_CTRL;
    148	uint32_t DCHUBBUB_DET2_CTRL;
    149	uint32_t DCHUBBUB_DET3_CTRL;
    150	uint32_t DCHUBBUB_COMPBUF_CTRL;
    151	uint32_t COMPBUF_RESERVED_SPACE;
    152	uint32_t DCHUBBUB_DEBUG_CTRL_0;
    153	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;
    154	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;
    155	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;
    156	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;
    157	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;
    158	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
    159	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
    160	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
    161};
    162
    163/* set field name */
    164#define HUBBUB_SF(reg_name, field_name, post_fix)\
    165	.field_name = reg_name ## __ ## field_name ## post_fix
    166
    167#define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\
    168		HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
    169		HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
    170		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
    171		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
    172		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
    173		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
    174		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
    175		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
    176		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
    177		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
    178		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
    179		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
    180		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
    181		HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
    182		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
    183		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
    184		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
    185		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh)
    186
    187#define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \
    188		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
    189		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
    190		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
    191		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
    192		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
    193		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
    194		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
    195		HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh)
    196
    197#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
    198		HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
    199		HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
    200		HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
    201		HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
    202		HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
    203		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
    204		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
    205		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)
    206
    207#define DCN_HUBBUB_REG_FIELD_LIST(type) \
    208		type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
    209		type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
    210		type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
    211		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
    212		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
    213		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
    214		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
    215		type DCHUBBUB_ARB_SAT_LEVEL;\
    216		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
    217		type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
    218		type DCHUBBUB_GLOBAL_SOFT_RESET; \
    219		type SDPIF_FB_TOP;\
    220		type SDPIF_FB_BASE;\
    221		type SDPIF_FB_OFFSET;\
    222		type SDPIF_AGP_BASE;\
    223		type SDPIF_AGP_BOT;\
    224		type SDPIF_AGP_TOP;\
    225		type FB_BASE;\
    226		type FB_TOP;\
    227		type FB_OFFSET;\
    228		type AGP_BOT;\
    229		type AGP_TOP;\
    230		type AGP_BASE;\
    231		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
    232		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\
    233		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\
    234		type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\
    235		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
    236		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
    237		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
    238		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
    239		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
    240		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
    241		type DCN_VM_FAULT_ADDR_MSB;\
    242		type DCN_VM_FAULT_ADDR_LSB;\
    243		type DCN_VM_ERROR_STATUS_CLEAR;\
    244		type DCN_VM_ERROR_STATUS_MODE;\
    245		type DCN_VM_ERROR_INTERRUPT_ENABLE;\
    246		type DCN_VM_RANGE_FAULT_DISABLE;\
    247		type DCN_VM_PRQ_FAULT_DISABLE;\
    248		type DCN_VM_ERROR_STATUS;\
    249		type DCN_VM_ERROR_VMID;\
    250		type DCN_VM_ERROR_TABLE_LEVEL;\
    251		type DCN_VM_ERROR_PIPE;\
    252		type DCN_VM_ERROR_INTERRUPT_STATUS
    253
    254#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
    255		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
    256		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\
    257		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\
    258		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\
    259		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\
    260		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\
    261		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
    262		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
    263
    264#define HUBBUB_HVM_REG_FIELD_LIST(type) \
    265		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
    266		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
    267		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
    268		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
    269		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
    270		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
    271		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
    272		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
    273		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
    274		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
    275		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
    276		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
    277		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
    278		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
    279		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
    280		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
    281		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
    282		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
    283		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
    284		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
    285		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
    286		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
    287		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
    288		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
    289		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
    290		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
    291		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
    292		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
    293		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
    294		type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
    295		type HOSTVM_INIT_REQ; \
    296		type HVM_GPUVMRET_PWR_REQ_DIS; \
    297		type HVM_GPUVMRET_FORCE_REQ; \
    298		type HVM_GPUVMRET_POWER_STATUS; \
    299		type HVM_DISPCLK_R_GATE_DIS; \
    300		type HVM_DISPCLK_G_GATE_DIS; \
    301		type HVM_DCFCLK_R_GATE_DIS; \
    302		type HVM_DCFCLK_G_GATE_DIS; \
    303		type TR_REQ_REQCLKREQ_MODE; \
    304		type TW_RSP_COMPCLKREQ_MODE; \
    305		type HOSTVM_PREFETCH_REQ; \
    306		type HOSTVM_POWERSTATUS; \
    307		type RIOMMU_ACTIVE; \
    308		type HOSTVM_PREFETCH_DONE
    309
    310#define HUBBUB_RET_REG_FIELD_LIST(type) \
    311		type DET_DEPTH;\
    312		type DET0_SIZE;\
    313		type DET1_SIZE;\
    314		type DET2_SIZE;\
    315		type DET3_SIZE;\
    316		type DET0_SIZE_CURRENT;\
    317		type DET1_SIZE_CURRENT;\
    318		type DET2_SIZE_CURRENT;\
    319		type DET3_SIZE_CURRENT;\
    320		type COMPBUF_SIZE;\
    321		type COMPBUF_SIZE_CURRENT;\
    322		type CONFIG_ERROR;\
    323		type COMPBUF_RESERVED_SPACE_64B;\
    324		type COMPBUF_RESERVED_SPACE_ZS;\
    325		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\
    326		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\
    327		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\
    328		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\
    329		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\
    330		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\
    331		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\
    332		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
    333
    334
    335struct dcn_hubbub_shift {
    336	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
    337	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
    338	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
    339	HUBBUB_RET_REG_FIELD_LIST(uint8_t);
    340};
    341
    342struct dcn_hubbub_mask {
    343	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
    344	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
    345	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
    346	HUBBUB_RET_REG_FIELD_LIST(uint32_t);
    347};
    348
    349struct dc;
    350
    351struct dcn10_hubbub {
    352	struct hubbub base;
    353	const struct dcn_hubbub_registers *regs;
    354	const struct dcn_hubbub_shift *shifts;
    355	const struct dcn_hubbub_mask *masks;
    356	unsigned int debug_test_index_pstate;
    357	struct dcn_watermark_set watermarks;
    358};
    359
    360void hubbub1_update_dchub(
    361	struct hubbub *hubbub,
    362	struct dchub_init_data *dh_data);
    363
    364bool hubbub1_verify_allow_pstate_change_high(
    365	struct hubbub *hubbub);
    366
    367void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
    368
    369bool hubbub1_program_watermarks(
    370		struct hubbub *hubbub,
    371		struct dcn_watermark_set *watermarks,
    372		unsigned int refclk_mhz,
    373		bool safe_to_lower);
    374
    375void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
    376
    377bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
    378
    379void hubbub1_toggle_watermark_change_req(
    380		struct hubbub *hubbub);
    381
    382void hubbub1_wm_read_state(struct hubbub *hubbub,
    383		struct dcn_hubbub_wm *wm);
    384
    385void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
    386void hubbub1_construct(struct hubbub *hubbub,
    387	struct dc_context *ctx,
    388	const struct dcn_hubbub_registers *hubbub_regs,
    389	const struct dcn_hubbub_shift *hubbub_shift,
    390	const struct dcn_hubbub_mask *hubbub_mask);
    391
    392bool hubbub1_program_urgent_watermarks(
    393		struct hubbub *hubbub,
    394		struct dcn_watermark_set *watermarks,
    395		unsigned int refclk_mhz,
    396		bool safe_to_lower);
    397bool hubbub1_program_stutter_watermarks(
    398		struct hubbub *hubbub,
    399		struct dcn_watermark_set *watermarks,
    400		unsigned int refclk_mhz,
    401		bool safe_to_lower);
    402bool hubbub1_program_pstate_watermarks(
    403		struct hubbub *hubbub,
    404		struct dcn_watermark_set *watermarks,
    405		unsigned int refclk_mhz,
    406		bool safe_to_lower);
    407
    408#endif