cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn10_init.c (5562B)


      1/*
      2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "hw_sequencer_private.h"
     27#include "dce110/dce110_hw_sequencer.h"
     28#include "dcn10_hw_sequencer.h"
     29#include "dcn20/dcn20_hwseq.h"
     30
     31static const struct hw_sequencer_funcs dcn10_funcs = {
     32	.program_gamut_remap = dcn10_program_gamut_remap,
     33	.init_hw = dcn10_init_hw,
     34	.power_down_on_boot = dcn10_power_down_on_boot,
     35	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
     36	.apply_ctx_for_surface = NULL,
     37	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
     38	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
     39	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
     40	.update_plane_addr = dcn10_update_plane_addr,
     41	.update_dchub = dcn10_update_dchub,
     42	.update_pending_status = dcn10_update_pending_status,
     43	.program_output_csc = dcn10_program_output_csc,
     44	.enable_accelerated_mode = dce110_enable_accelerated_mode,
     45	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
     46	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
     47	.update_info_frame = dce110_update_info_frame,
     48	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
     49	.enable_stream = dce110_enable_stream,
     50	.disable_stream = dce110_disable_stream,
     51	.unblank_stream = dcn10_unblank_stream,
     52	.blank_stream = dce110_blank_stream,
     53	.enable_audio_stream = dce110_enable_audio_stream,
     54	.disable_audio_stream = dce110_disable_audio_stream,
     55	.disable_plane = dcn10_disable_plane,
     56	.pipe_control_lock = dcn10_pipe_control_lock,
     57	.cursor_lock = dcn10_cursor_lock,
     58	.interdependent_update_lock = dcn10_lock_all_pipes,
     59	.prepare_bandwidth = dcn10_prepare_bandwidth,
     60	.optimize_bandwidth = dcn10_optimize_bandwidth,
     61	.set_drr = dcn10_set_drr,
     62	.get_position = dcn10_get_position,
     63	.set_static_screen_control = dcn10_set_static_screen_control,
     64	.setup_stereo = dcn10_setup_stereo,
     65	.set_avmute = dce110_set_avmute,
     66	.log_hw_state = dcn10_log_hw_state,
     67	.get_hw_state = dcn10_get_hw_state,
     68	.clear_status_bits = dcn10_clear_status_bits,
     69	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
     70	.edp_backlight_control = dce110_edp_backlight_control,
     71	.edp_power_control = dce110_edp_power_control,
     72	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
     73	.set_cursor_position = dcn10_set_cursor_position,
     74	.set_cursor_attribute = dcn10_set_cursor_attribute,
     75	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
     76	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
     77	.set_clock = dcn10_set_clock,
     78	.get_clock = dcn10_get_clock,
     79	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
     80	.calc_vupdate_position = dcn10_calc_vupdate_position,
     81	.power_down = dce110_power_down,
     82	.set_backlight_level = dce110_set_backlight_level,
     83	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
     84	.set_pipe = dce110_set_pipe,
     85	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
     86	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
     87};
     88
     89static const struct hwseq_private_funcs dcn10_private_funcs = {
     90	.init_pipes = dcn10_init_pipes,
     91	.update_plane_addr = dcn10_update_plane_addr,
     92	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
     93	.program_pipe = dcn10_program_pipe,
     94	.update_mpcc = dcn10_update_mpcc,
     95	.set_input_transfer_func = dcn10_set_input_transfer_func,
     96	.set_output_transfer_func = dcn10_set_output_transfer_func,
     97	.power_down = dce110_power_down,
     98	.enable_display_power_gating = dcn10_dummy_display_power_gating,
     99	.blank_pixel_data = dcn10_blank_pixel_data,
    100	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
    101	.enable_stream_timing = dcn10_enable_stream_timing,
    102	.edp_backlight_control = dce110_edp_backlight_control,
    103	.disable_stream_gating = NULL,
    104	.enable_stream_gating = NULL,
    105	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
    106	.did_underflow_occur = dcn10_did_underflow_occur,
    107	.init_blank = NULL,
    108	.disable_vga = dcn10_disable_vga,
    109	.bios_golden_init = dcn10_bios_golden_init,
    110	.plane_atomic_disable = dcn10_plane_atomic_disable,
    111	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
    112	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
    113	.dpp_pg_control = dcn10_dpp_pg_control,
    114	.hubp_pg_control = dcn10_hubp_pg_control,
    115	.dsc_pg_control = NULL,
    116	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
    117	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
    118};
    119
    120void dcn10_hw_sequencer_construct(struct dc *dc)
    121{
    122	dc->hwss = dcn10_funcs;
    123	dc->hwseq->funcs = dcn10_private_funcs;
    124}