cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn20_dsc.c (30906B)


      1/*
      2 * Copyright 2017 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include <drm/display/drm_dsc_helper.h>
     27
     28#include "reg_helper.h"
     29#include "dcn20_dsc.h"
     30#include "dsc/dscc_types.h"
     31
     32static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
     33static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
     34			struct dsc_optc_config *dsc_optc_cfg);
     35static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
     36static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
     37static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
     38static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple);
     39static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth);
     40
     41/* Object I/F functions */
     42static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
     43static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
     44static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
     45static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
     46		struct dsc_optc_config *dsc_optc_cfg);
     47static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
     48static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
     49static void dsc2_disable(struct display_stream_compressor *dsc);
     50static void dsc2_disconnect(struct display_stream_compressor *dsc);
     51
     52const struct dsc_funcs dcn20_dsc_funcs = {
     53	.dsc_get_enc_caps = dsc2_get_enc_caps,
     54	.dsc_read_state = dsc2_read_state,
     55	.dsc_validate_stream = dsc2_validate_stream,
     56	.dsc_set_config = dsc2_set_config,
     57	.dsc_get_packed_pps = dsc2_get_packed_pps,
     58	.dsc_enable = dsc2_enable,
     59	.dsc_disable = dsc2_disable,
     60	.dsc_disconnect = dsc2_disconnect,
     61};
     62
     63/* Macro definitios for REG_SET macros*/
     64#define CTX \
     65	dsc20->base.ctx
     66
     67#define REG(reg)\
     68	dsc20->dsc_regs->reg
     69
     70#undef FN
     71#define FN(reg_name, field_name) \
     72	dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
     73#define DC_LOGGER \
     74	dsc->ctx->logger
     75
     76enum dsc_bits_per_comp {
     77	DSC_BPC_8 = 8,
     78	DSC_BPC_10 = 10,
     79	DSC_BPC_12 = 12,
     80	DSC_BPC_UNKNOWN
     81};
     82
     83/* API functions (external or via structure->function_pointer) */
     84
     85void dsc2_construct(struct dcn20_dsc *dsc,
     86		struct dc_context *ctx,
     87		int inst,
     88		const struct dcn20_dsc_registers *dsc_regs,
     89		const struct dcn20_dsc_shift *dsc_shift,
     90		const struct dcn20_dsc_mask *dsc_mask)
     91{
     92	dsc->base.ctx = ctx;
     93	dsc->base.inst = inst;
     94	dsc->base.funcs = &dcn20_dsc_funcs;
     95
     96	dsc->dsc_regs = dsc_regs;
     97	dsc->dsc_shift = dsc_shift;
     98	dsc->dsc_mask = dsc_mask;
     99
    100	dsc->max_image_width = 5184;
    101}
    102
    103
    104#define DCN20_MAX_PIXEL_CLOCK_Mhz      1188
    105#define DCN20_MAX_DISPLAY_CLOCK_Mhz    1200
    106
    107/* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
    108 * can be doubled, tripled etc. by using additional DSC engines.
    109 */
    110static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
    111{
    112	dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
    113
    114	dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
    115	dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
    116	dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
    117	dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
    118
    119	dsc_enc_caps->lb_bit_depth = 13;
    120	dsc_enc_caps->is_block_pred_supported = true;
    121
    122	dsc_enc_caps->color_formats.bits.RGB = 1;
    123	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
    124	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
    125	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
    126	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
    127
    128	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
    129	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
    130	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
    131
    132	/* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
    133	 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
    134	 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
    135	 * be sufficient to process the input pixel rate fed into a single DSC engine.
    136	 */
    137	dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
    138
    139	/* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
    140	 * throughput and number of slices, but also introduces a lower limit of 2 slices
    141	 */
    142	if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
    143		dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
    144		dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
    145		dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
    146	}
    147
    148	// TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM.
    149	dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
    150	dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
    151}
    152
    153
    154/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
    155 * into a dcn_dsc_state struct.
    156 */
    157static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
    158{
    159	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    160
    161	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
    162	REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
    163	REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
    164	REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
    165	REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
    166	REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
    167	REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
    168	REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
    169	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
    170		DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
    171}
    172
    173
    174static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
    175{
    176	struct dsc_optc_config dsc_optc_cfg;
    177	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    178
    179	if (dsc_cfg->pic_width > dsc20->max_image_width)
    180		return false;
    181
    182	return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
    183}
    184
    185
    186static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
    187{
    188	DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
    189	DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
    190	DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
    191		config->dc_dsc_cfg.bits_per_pixel,
    192		config->dc_dsc_cfg.bits_per_pixel / 16,
    193		((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
    194	DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
    195}
    196
    197static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
    198		struct dsc_optc_config *dsc_optc_cfg)
    199{
    200	bool is_config_ok;
    201	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    202
    203	DC_LOG_DSC(" ");
    204	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
    205	dsc_config_log(dsc, dsc_cfg);
    206	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
    207	ASSERT(is_config_ok);
    208	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
    209	dsc_log_pps(dsc, &dsc20->reg_vals.pps);
    210	dsc_write_to_registers(dsc, &dsc20->reg_vals);
    211}
    212
    213
    214static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
    215{
    216	bool is_config_ok;
    217	struct dsc_reg_values dsc_reg_vals;
    218	struct dsc_optc_config dsc_optc_cfg;
    219
    220	memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
    221	memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
    222
    223	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
    224	dsc_config_log(dsc, dsc_cfg);
    225	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
    226	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
    227	ASSERT(is_config_ok);
    228	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
    229	dsc_log_pps(dsc, &dsc_reg_vals.pps);
    230
    231	return is_config_ok;
    232}
    233
    234
    235static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
    236{
    237	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    238	int dsc_clock_en;
    239	int dsc_fw_config;
    240	int enabled_opp_pipe;
    241
    242	DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
    243
    244	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
    245	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
    246	if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
    247		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
    248		ASSERT(0);
    249	}
    250
    251	REG_UPDATE(DSC_TOP_CONTROL,
    252		DSC_CLOCK_EN, 1);
    253
    254	REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
    255		DSCRM_DSC_FORWARD_EN, 1,
    256		DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
    257}
    258
    259
    260static void dsc2_disable(struct display_stream_compressor *dsc)
    261{
    262	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    263	int dsc_clock_en;
    264	int dsc_fw_config;
    265	int enabled_opp_pipe;
    266
    267	DC_LOG_DSC("disable DSC %d", dsc->inst);
    268
    269	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
    270	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
    271	if (!dsc_clock_en || !dsc_fw_config) {
    272		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe);
    273		ASSERT(0);
    274	}
    275
    276	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
    277		DSCRM_DSC_FORWARD_EN, 0);
    278
    279	REG_UPDATE(DSC_TOP_CONTROL,
    280		DSC_CLOCK_EN, 0);
    281}
    282
    283static void dsc2_disconnect(struct display_stream_compressor *dsc)
    284{
    285	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    286
    287	DC_LOG_DSC("disconnect DSC %d", dsc->inst);
    288
    289	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
    290		DSCRM_DSC_FORWARD_EN, 0);
    291}
    292
    293/* This module's internal functions */
    294static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
    295{
    296	int i;
    297	int bits_per_pixel = pps->bits_per_pixel;
    298
    299	DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
    300	DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
    301	DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
    302	DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
    303	DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
    304	DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
    305	DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
    306	DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
    307	DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
    308	DC_LOG_DSC("\tpic_height %d", pps->pic_height);
    309	DC_LOG_DSC("\tpic_width %d", pps->pic_width);
    310	DC_LOG_DSC("\tslice_height %d", pps->slice_height);
    311	DC_LOG_DSC("\tslice_width %d", pps->slice_width);
    312	DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
    313	DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
    314	DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
    315	DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
    316	DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
    317	DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
    318	DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
    319	DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
    320	DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
    321	DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
    322	DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
    323	DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
    324	DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
    325	/* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
    326	DC_LOG_DSC("\tnative_420 %d", pps->native_420);
    327	DC_LOG_DSC("\tnative_422 %d", pps->native_422);
    328	DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
    329	DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
    330	DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
    331	DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
    332	DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
    333	DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
    334	DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
    335	DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
    336	DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
    337
    338	for (i = 0; i < NUM_BUF_RANGES - 1; i++)
    339		DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
    340
    341	for (i = 0; i < NUM_BUF_RANGES; i++) {
    342		DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
    343		DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
    344		DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
    345	}
    346}
    347
    348static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
    349			struct dsc_optc_config *dsc_optc_cfg)
    350{
    351	struct dsc_parameters dsc_params;
    352
    353	/* Validate input parameters */
    354	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
    355	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
    356	ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
    357	ASSERT(dsc_cfg->pic_width);
    358	ASSERT(dsc_cfg->pic_height);
    359	ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
    360		  (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
    361		(dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
    362		  ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
    363		    dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
    364	ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
    365
    366	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
    367		!(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
    368		!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
    369		!((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
    370			8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
    371		(dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
    372			((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
    373			dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
    374		!(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
    375		dm_output_to_console("%s: Invalid parameters\n", __func__);
    376		return false;
    377	}
    378
    379	dsc_init_reg_values(dsc_reg_vals);
    380
    381	/* Copy input config */
    382	dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
    383	dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
    384	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
    385	dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
    386	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
    387	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
    388	dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
    389	dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
    390	dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
    391	dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
    392	dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
    393
    394	// TODO: in addition to validating slice height (pic height must be divisible by slice height),
    395	// see what happens when the same condition doesn't apply for slice_width/pic_width.
    396	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
    397	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
    398
    399	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
    400	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
    401		dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
    402		return false;
    403	}
    404
    405	dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
    406	if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
    407		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
    408	else
    409		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
    410
    411	dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
    412	dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
    413	dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
    414	dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
    415
    416	if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
    417		dm_output_to_console("%s: DSC config failed\n", __func__);
    418		return false;
    419	}
    420
    421	dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
    422
    423	dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
    424	dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
    425	dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
    426					dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
    427					dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
    428
    429	return true;
    430}
    431
    432
    433static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
    434{
    435	enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
    436
    437	/* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
    438
    439	switch (dc_pix_enc) {
    440	case PIXEL_ENCODING_RGB:
    441		dsc_pix_fmt = DSC_PIXFMT_RGB;
    442		break;
    443	case PIXEL_ENCODING_YCBCR422:
    444		if (is_ycbcr422_simple)
    445			dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
    446		else
    447			dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
    448		break;
    449	case PIXEL_ENCODING_YCBCR444:
    450		dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
    451		break;
    452	case PIXEL_ENCODING_YCBCR420:
    453		dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
    454		break;
    455	default:
    456		dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
    457		break;
    458	}
    459
    460	ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
    461	return dsc_pix_fmt;
    462}
    463
    464
    465static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
    466{
    467	enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
    468
    469	switch (dc_color_depth) {
    470	case COLOR_DEPTH_888:
    471		bpc = DSC_BPC_8;
    472		break;
    473	case COLOR_DEPTH_101010:
    474		bpc = DSC_BPC_10;
    475		break;
    476	case COLOR_DEPTH_121212:
    477		bpc = DSC_BPC_12;
    478		break;
    479	default:
    480		bpc = DSC_BPC_UNKNOWN;
    481		break;
    482	}
    483
    484	return bpc;
    485}
    486
    487
    488static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
    489{
    490	int i;
    491
    492	memset(reg_vals, 0, sizeof(struct dsc_reg_values));
    493
    494	/* Non-PPS values */
    495	reg_vals->dsc_clock_enable            = 1;
    496	reg_vals->dsc_clock_gating_disable    = 0;
    497	reg_vals->underflow_recovery_en       = 0;
    498	reg_vals->underflow_occurred_int_en   = 0;
    499	reg_vals->underflow_occurred_status   = 0;
    500	reg_vals->ich_reset_at_eol            = 0;
    501	reg_vals->alternate_ich_encoding_en   = 0;
    502	reg_vals->rc_buffer_model_size        = 0;
    503	/*reg_vals->disable_ich                 = 0;*/
    504	reg_vals->dsc_dbg_en                  = 0;
    505
    506	for (i = 0; i < 4; i++)
    507		reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
    508
    509	/* PPS values */
    510	reg_vals->pps.dsc_version_minor           = 2;
    511	reg_vals->pps.dsc_version_major           = 1;
    512	reg_vals->pps.line_buf_depth              = 9;
    513	reg_vals->pps.bits_per_component          = 8;
    514	reg_vals->pps.block_pred_enable           = 1;
    515	reg_vals->pps.slice_chunk_size            = 0;
    516	reg_vals->pps.pic_width                   = 0;
    517	reg_vals->pps.pic_height                  = 0;
    518	reg_vals->pps.slice_width                 = 0;
    519	reg_vals->pps.slice_height                = 0;
    520	reg_vals->pps.initial_xmit_delay          = 170;
    521	reg_vals->pps.initial_dec_delay           = 0;
    522	reg_vals->pps.initial_scale_value         = 0;
    523	reg_vals->pps.scale_increment_interval    = 0;
    524	reg_vals->pps.scale_decrement_interval    = 0;
    525	reg_vals->pps.nfl_bpg_offset              = 0;
    526	reg_vals->pps.slice_bpg_offset            = 0;
    527	reg_vals->pps.nsl_bpg_offset              = 0;
    528	reg_vals->pps.initial_offset              = 6144;
    529	reg_vals->pps.final_offset                = 0;
    530	reg_vals->pps.flatness_min_qp             = 3;
    531	reg_vals->pps.flatness_max_qp             = 12;
    532	reg_vals->pps.rc_model_size               = 8192;
    533	reg_vals->pps.rc_edge_factor              = 6;
    534	reg_vals->pps.rc_quant_incr_limit0        = 11;
    535	reg_vals->pps.rc_quant_incr_limit1        = 11;
    536	reg_vals->pps.rc_tgt_offset_low           = 3;
    537	reg_vals->pps.rc_tgt_offset_high          = 3;
    538}
    539
    540/* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
    541 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
    542 * affects non-PPS register values.
    543 */
    544static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
    545{
    546	int i;
    547
    548	reg_vals->pps = dsc_params->pps;
    549
    550	// pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
    551	for (i = 0; i < NUM_BUF_RANGES - 1; i++)
    552		reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
    553
    554	reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
    555}
    556
    557static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
    558{
    559	uint32_t temp_int;
    560	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
    561
    562	REG_SET(DSC_DEBUG_CONTROL, 0,
    563		DSC_DBG_EN, reg_vals->dsc_dbg_en);
    564
    565	// dsccif registers
    566	REG_SET_5(DSCCIF_CONFIG0, 0,
    567		INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
    568		INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
    569		INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
    570		INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
    571		DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
    572
    573	REG_SET_2(DSCCIF_CONFIG1, 0,
    574		PIC_WIDTH, reg_vals->pps.pic_width,
    575		PIC_HEIGHT, reg_vals->pps.pic_height);
    576
    577	// dscc registers
    578	REG_SET_4(DSCC_CONFIG0, 0,
    579		ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol,
    580		NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
    581		ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
    582		NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
    583
    584	REG_SET(DSCC_CONFIG1, 0,
    585			DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
    586	/*REG_SET_2(DSCC_CONFIG1, 0,
    587		DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
    588		DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
    589
    590	REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
    591		DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
    592		DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
    593		DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
    594		DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
    595
    596	REG_SET_3(DSCC_PPS_CONFIG0, 0,
    597		DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
    598		LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
    599		DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
    600
    601	if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
    602		temp_int = reg_vals->bpp_x32;
    603	else
    604		temp_int = reg_vals->bpp_x32 >> 1;
    605
    606	REG_SET_7(DSCC_PPS_CONFIG1, 0,
    607		BITS_PER_PIXEL, temp_int,
    608		SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
    609		CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
    610		BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
    611		NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
    612		NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
    613		CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
    614
    615	REG_SET_2(DSCC_PPS_CONFIG2, 0,
    616		PIC_WIDTH, reg_vals->pps.pic_width,
    617		PIC_HEIGHT, reg_vals->pps.pic_height);
    618
    619	REG_SET_2(DSCC_PPS_CONFIG3, 0,
    620		SLICE_WIDTH, reg_vals->pps.slice_width,
    621		SLICE_HEIGHT, reg_vals->pps.slice_height);
    622
    623	REG_SET(DSCC_PPS_CONFIG4, 0,
    624		INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
    625
    626	REG_SET_2(DSCC_PPS_CONFIG5, 0,
    627		INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
    628		SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
    629
    630	REG_SET_3(DSCC_PPS_CONFIG6, 0,
    631		SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
    632		FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
    633		SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
    634
    635	REG_SET_2(DSCC_PPS_CONFIG7, 0,
    636		NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
    637		SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
    638
    639	REG_SET_2(DSCC_PPS_CONFIG8, 0,
    640		NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
    641		SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
    642
    643	REG_SET_2(DSCC_PPS_CONFIG9, 0,
    644		INITIAL_OFFSET, reg_vals->pps.initial_offset,
    645		FINAL_OFFSET, reg_vals->pps.final_offset);
    646
    647	REG_SET_3(DSCC_PPS_CONFIG10, 0,
    648		FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
    649		FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
    650		RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
    651
    652	REG_SET_5(DSCC_PPS_CONFIG11, 0,
    653		RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
    654		RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
    655		RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
    656		RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
    657		RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
    658
    659	REG_SET_4(DSCC_PPS_CONFIG12, 0,
    660		RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
    661		RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
    662		RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
    663		RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
    664
    665	REG_SET_4(DSCC_PPS_CONFIG13, 0,
    666		RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
    667		RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
    668		RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
    669		RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
    670
    671	REG_SET_4(DSCC_PPS_CONFIG14, 0,
    672		RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
    673		RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
    674		RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
    675		RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
    676
    677	REG_SET_5(DSCC_PPS_CONFIG15, 0,
    678		RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
    679		RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
    680		RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
    681		RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
    682		RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
    683
    684	REG_SET_6(DSCC_PPS_CONFIG16, 0,
    685		RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
    686		RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
    687		RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
    688		RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
    689		RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
    690		RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
    691
    692	REG_SET_6(DSCC_PPS_CONFIG17, 0,
    693		RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
    694		RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
    695		RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
    696		RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
    697		RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
    698		RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
    699
    700	REG_SET_6(DSCC_PPS_CONFIG18, 0,
    701		RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
    702		RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
    703		RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
    704		RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
    705		RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
    706		RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
    707
    708	REG_SET_6(DSCC_PPS_CONFIG19, 0,
    709		RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
    710		RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
    711		RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
    712		RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
    713		RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
    714		RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
    715
    716	REG_SET_6(DSCC_PPS_CONFIG20, 0,
    717		RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
    718		RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
    719		RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
    720		RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
    721		RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
    722		RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
    723
    724	REG_SET_6(DSCC_PPS_CONFIG21, 0,
    725		RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
    726		RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
    727		RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
    728		RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
    729		RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
    730		RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
    731
    732	REG_SET_6(DSCC_PPS_CONFIG22, 0,
    733		RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
    734		RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
    735		RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
    736		RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
    737		RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
    738		RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
    739
    740}
    741