cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dcn20_dsc.h (25123B)


      1/* Copyright 2017 Advanced Micro Devices, Inc.
      2 *
      3 * Permission is hereby granted, free of charge, to any person obtaining a
      4 * copy of this software and associated documentation files (the "Software"),
      5 * to deal in the Software without restriction, including without limitation
      6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      7 * and/or sell copies of the Software, and to permit persons to whom the
      8 * Software is furnished to do so, subject to the following conditions:
      9 *
     10 * The above copyright notice and this permission notice shall be included in
     11 * all copies or substantial portions of the Software.
     12 *
     13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     19 * OTHER DEALINGS IN THE SOFTWARE.
     20 *
     21 * Authors: AMD
     22 *
     23 */
     24#ifndef __DCN20_DSC_H__
     25#define __DCN20_DSC_H__
     26
     27#include "dsc.h"
     28#include "dsc/dscc_types.h"
     29#include <drm/display/drm_dsc.h>
     30
     31#define TO_DCN20_DSC(dsc)\
     32	container_of(dsc, struct dcn20_dsc, base)
     33
     34#define DSC_REG_LIST_DCN20(id) \
     35	SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
     36	SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\
     37	SRI(DSCC_CONFIG0, DSCC, id),\
     38	SRI(DSCC_CONFIG1, DSCC, id),\
     39	SRI(DSCC_STATUS, DSCC, id),\
     40	SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\
     41	SRI(DSCC_PPS_CONFIG0, DSCC, id),\
     42	SRI(DSCC_PPS_CONFIG1, DSCC, id),\
     43	SRI(DSCC_PPS_CONFIG2, DSCC, id),\
     44	SRI(DSCC_PPS_CONFIG3, DSCC, id),\
     45	SRI(DSCC_PPS_CONFIG4, DSCC, id),\
     46	SRI(DSCC_PPS_CONFIG5, DSCC, id),\
     47	SRI(DSCC_PPS_CONFIG6, DSCC, id),\
     48	SRI(DSCC_PPS_CONFIG7, DSCC, id),\
     49	SRI(DSCC_PPS_CONFIG8, DSCC, id),\
     50	SRI(DSCC_PPS_CONFIG9, DSCC, id),\
     51	SRI(DSCC_PPS_CONFIG10, DSCC, id),\
     52	SRI(DSCC_PPS_CONFIG11, DSCC, id),\
     53	SRI(DSCC_PPS_CONFIG12, DSCC, id),\
     54	SRI(DSCC_PPS_CONFIG13, DSCC, id),\
     55	SRI(DSCC_PPS_CONFIG14, DSCC, id),\
     56	SRI(DSCC_PPS_CONFIG15, DSCC, id),\
     57	SRI(DSCC_PPS_CONFIG16, DSCC, id),\
     58	SRI(DSCC_PPS_CONFIG17, DSCC, id),\
     59	SRI(DSCC_PPS_CONFIG18, DSCC, id),\
     60	SRI(DSCC_PPS_CONFIG19, DSCC, id),\
     61	SRI(DSCC_PPS_CONFIG20, DSCC, id),\
     62	SRI(DSCC_PPS_CONFIG21, DSCC, id),\
     63	SRI(DSCC_PPS_CONFIG22, DSCC, id),\
     64	SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\
     65	SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\
     66	SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\
     67	SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\
     68	SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\
     69	SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\
     70	SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\
     71	SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\
     72	SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\
     73	SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
     74	SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
     75	SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
     76	SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
     77	SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
     78	SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
     79	SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
     80	SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
     81	SRI(DSCCIF_CONFIG0, DSCCIF, id),\
     82	SRI(DSCCIF_CONFIG1, DSCCIF, id),\
     83	SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
     84
     85
     86#define DSC_SF(reg_name, field_name, post_fix)\
     87	.field_name = reg_name ## __ ## field_name ## post_fix
     88
     89//Used in resolving the corner case with duplicate field name
     90#define DSC2_SF(reg_name, field_name, post_fix)\
     91	.field_name = reg_name ## _ ## field_name ## post_fix
     92
     93#define DSC_REG_LIST_SH_MASK_DCN20(mask_sh)\
     94	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
     95	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
     96	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
     97	DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
     98	DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
     99	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
    100	DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
    101	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
    102	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
    103	/*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
    104	DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
    105	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
    106	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
    107	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
    108	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
    109	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
    110	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
    111	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
    112	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
    113	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
    114	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
    115	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
    116	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
    117	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    118	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    119	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    120	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    121	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
    122	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
    123	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
    124	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
    125	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    126	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    127	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    128	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
    129	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
    130	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
    131	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
    132	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
    133	DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
    134	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
    135	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
    136	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
    137	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
    138	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
    139	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
    140	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
    141	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
    142	DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
    143	DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
    144	DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
    145	DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
    146	DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
    147	DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
    148	DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
    149	DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
    150	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
    151	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
    152	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
    153	DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
    154	DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
    155	DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
    156	DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
    157	DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
    158	DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
    159	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \
    160	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
    161	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
    162	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
    163	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
    164	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
    165	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
    166	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
    167	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
    168	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
    169	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
    170	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
    171	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
    172	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
    173	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
    174	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
    175	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
    176	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
    177	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
    178	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
    179	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
    180	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
    181	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
    182	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
    183	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
    184	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
    185	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
    186	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
    187	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
    188	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
    189	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
    190	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
    191	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
    192	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
    193	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
    194	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
    195	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
    196	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
    197	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
    198	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
    199	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
    200	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
    201	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
    202	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
    203	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
    204	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
    205	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
    206	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
    207	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
    208	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
    209	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
    210	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
    211	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
    212	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
    213	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
    214	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
    215	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
    216	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
    217	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
    218	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
    219	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
    220	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
    221	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
    222	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
    223	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
    224	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
    225	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
    226	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
    227	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \
    228	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \
    229	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \
    230	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \
    231	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \
    232	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \
    233	DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
    234	DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
    235	DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
    236	DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
    237	DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
    238	DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
    239	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
    240	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
    241	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
    242	DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
    243	DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
    244	DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
    245	DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
    246	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
    247	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
    248	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
    249	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
    250	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
    251	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
    252	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
    253	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
    254	DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
    255	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
    256	DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \
    257	DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \
    258	DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
    259	DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)
    260
    261
    262
    263#define DSC_FIELD_LIST_DCN20(type)\
    264	type DSC_CLOCK_EN; \
    265	type DSC_DISPCLK_R_GATE_DIS; \
    266	type DSC_DSCCLK_R_GATE_DIS; \
    267	type DSC_DBG_EN; \
    268	type DSC_TEST_CLOCK_MUX_SEL; \
    269	type ICH_RESET_AT_END_OF_LINE; \
    270	type NUMBER_OF_SLICES_PER_LINE; \
    271	type ALTERNATE_ICH_ENCODING_EN; \
    272	type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
    273	type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
    274	/*type DSCC_DISABLE_ICH;*/ \
    275	type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
    276	type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
    277	type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
    278	type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED; \
    279	type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED; \
    280	type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED; \
    281	type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED; \
    282	type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED; \
    283	type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED; \
    284	type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED; \
    285	type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED; \
    286	type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED; \
    287	type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED; \
    288	type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN; \
    289	type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN; \
    290	type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN; \
    291	type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN; \
    292	type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN; \
    293	type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN; \
    294	type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN; \
    295	type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN; \
    296	type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN; \
    297	type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN; \
    298	type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN; \
    299	type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN; \
    300	type DSC_VERSION_MINOR; \
    301	type DSC_VERSION_MAJOR; \
    302	type PPS_IDENTIFIER; \
    303	type LINEBUF_DEPTH; \
    304	type DSCC_PPS_CONFIG0__BITS_PER_COMPONENT; \
    305	type BITS_PER_PIXEL; \
    306	type VBR_ENABLE; \
    307	type SIMPLE_422; \
    308	type CONVERT_RGB; \
    309	type BLOCK_PRED_ENABLE; \
    310	type NATIVE_422; \
    311	type NATIVE_420; \
    312	type CHUNK_SIZE; \
    313	type PIC_WIDTH; \
    314	type PIC_HEIGHT; \
    315	type SLICE_WIDTH; \
    316	type SLICE_HEIGHT; \
    317	type INITIAL_XMIT_DELAY; \
    318	type INITIAL_DEC_DELAY; \
    319	type INITIAL_SCALE_VALUE; \
    320	type SCALE_INCREMENT_INTERVAL; \
    321	type SCALE_DECREMENT_INTERVAL; \
    322	type FIRST_LINE_BPG_OFFSET; \
    323	type SECOND_LINE_BPG_OFFSET; \
    324	type NFL_BPG_OFFSET; \
    325	type SLICE_BPG_OFFSET; \
    326	type NSL_BPG_OFFSET; \
    327	type SECOND_LINE_OFFSET_ADJ; \
    328	type INITIAL_OFFSET; \
    329	type FINAL_OFFSET; \
    330	type FLATNESS_MIN_QP; \
    331	type FLATNESS_MAX_QP; \
    332	type RC_MODEL_SIZE; \
    333	type RC_EDGE_FACTOR; \
    334	type RC_QUANT_INCR_LIMIT0; \
    335	type RC_QUANT_INCR_LIMIT1; \
    336	type RC_TGT_OFFSET_LO; \
    337	type RC_TGT_OFFSET_HI; \
    338	type RC_BUF_THRESH0; \
    339	type RC_BUF_THRESH1; \
    340	type RC_BUF_THRESH2; \
    341	type RC_BUF_THRESH3; \
    342	type RC_BUF_THRESH4; \
    343	type RC_BUF_THRESH5; \
    344	type RC_BUF_THRESH6; \
    345	type RC_BUF_THRESH7; \
    346	type RC_BUF_THRESH8; \
    347	type RC_BUF_THRESH9; \
    348	type RC_BUF_THRESH10; \
    349	type RC_BUF_THRESH11; \
    350	type RC_BUF_THRESH12; \
    351	type RC_BUF_THRESH13; \
    352	type RANGE_MIN_QP0; \
    353	type RANGE_MAX_QP0; \
    354	type RANGE_BPG_OFFSET0; \
    355	type RANGE_MIN_QP1; \
    356	type RANGE_MAX_QP1; \
    357	type RANGE_BPG_OFFSET1; \
    358	type RANGE_MIN_QP2; \
    359	type RANGE_MAX_QP2; \
    360	type RANGE_BPG_OFFSET2; \
    361	type RANGE_MIN_QP3; \
    362	type RANGE_MAX_QP3; \
    363	type RANGE_BPG_OFFSET3; \
    364	type RANGE_MIN_QP4; \
    365	type RANGE_MAX_QP4; \
    366	type RANGE_BPG_OFFSET4; \
    367	type RANGE_MIN_QP5; \
    368	type RANGE_MAX_QP5; \
    369	type RANGE_BPG_OFFSET5; \
    370	type RANGE_MIN_QP6; \
    371	type RANGE_MAX_QP6; \
    372	type RANGE_BPG_OFFSET6; \
    373	type RANGE_MIN_QP7; \
    374	type RANGE_MAX_QP7; \
    375	type RANGE_BPG_OFFSET7; \
    376	type RANGE_MIN_QP8; \
    377	type RANGE_MAX_QP8; \
    378	type RANGE_BPG_OFFSET8; \
    379	type RANGE_MIN_QP9; \
    380	type RANGE_MAX_QP9; \
    381	type RANGE_BPG_OFFSET9; \
    382	type RANGE_MIN_QP10; \
    383	type RANGE_MAX_QP10; \
    384	type RANGE_BPG_OFFSET10; \
    385	type RANGE_MIN_QP11; \
    386	type RANGE_MAX_QP11; \
    387	type RANGE_BPG_OFFSET11; \
    388	type RANGE_MIN_QP12; \
    389	type RANGE_MAX_QP12; \
    390	type RANGE_BPG_OFFSET12; \
    391	type RANGE_MIN_QP13; \
    392	type RANGE_MAX_QP13; \
    393	type RANGE_BPG_OFFSET13; \
    394	type RANGE_MIN_QP14; \
    395	type RANGE_MAX_QP14; \
    396	type RANGE_BPG_OFFSET14; \
    397	type DSCC_DEFAULT_MEM_LOW_POWER_STATE; \
    398	type DSCC_MEM_PWR_FORCE; \
    399	type DSCC_MEM_PWR_DIS; \
    400	type DSCC_MEM_PWR_STATE; \
    401	type DSCC_NATIVE_422_MEM_PWR_FORCE; \
    402	type DSCC_NATIVE_422_MEM_PWR_DIS; \
    403	type DSCC_NATIVE_422_MEM_PWR_STATE; \
    404	type DSCC_R_Y_SQUARED_ERROR_LOWER; \
    405	type DSCC_R_Y_SQUARED_ERROR_UPPER; \
    406	type DSCC_G_CB_SQUARED_ERROR_LOWER; \
    407	type DSCC_G_CB_SQUARED_ERROR_UPPER; \
    408	type DSCC_B_CR_SQUARED_ERROR_LOWER; \
    409	type DSCC_B_CR_SQUARED_ERROR_UPPER; \
    410	type DSCC_R_Y_MAX_ABS_ERROR; \
    411	type DSCC_G_CB_MAX_ABS_ERROR; \
    412	type DSCC_B_CR_MAX_ABS_ERROR; \
    413	type DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL; \
    414	type DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL; \
    415	type DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL; \
    416	type DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL; \
    417	type DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL; \
    418	type DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; \
    419	type DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; \
    420	type DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; \
    421	type DSCC_UPDATE_PENDING_STATUS; \
    422	type DSCC_UPDATE_TAKEN_STATUS; \
    423	type DSCC_UPDATE_TAKEN_ACK; \
    424	type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
    425	type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
    426	type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
    427	type DSCC_RATE_BUFFER3_FULLNESS_LEVEL; \
    428	type DSCC_RATE_CONTROL_BUFFER0_FULLNESS_LEVEL; \
    429	type DSCC_RATE_CONTROL_BUFFER1_FULLNESS_LEVEL; \
    430	type DSCC_RATE_CONTROL_BUFFER2_FULLNESS_LEVEL; \
    431	type DSCC_RATE_CONTROL_BUFFER3_FULLNESS_LEVEL; \
    432	type DSCC_RATE_BUFFER0_INITIAL_XMIT_DELAY_REACHED; \
    433	type DSCC_RATE_BUFFER1_INITIAL_XMIT_DELAY_REACHED; \
    434	type DSCC_RATE_BUFFER2_INITIAL_XMIT_DELAY_REACHED; \
    435	type DSCC_RATE_BUFFER3_INITIAL_XMIT_DELAY_REACHED; \
    436	type INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN; \
    437	type INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN; \
    438	type INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS; \
    439	type INPUT_PIXEL_FORMAT; \
    440	type DSCCIF_CONFIG0__BITS_PER_COMPONENT; \
    441	type DOUBLE_BUFFER_REG_UPDATE_PENDING; \
    442	type DSCCIF_UPDATE_PENDING_STATUS; \
    443	type DSCCIF_UPDATE_TAKEN_STATUS; \
    444	type DSCCIF_UPDATE_TAKEN_ACK; \
    445	type DSCRM_DSC_FORWARD_EN; \
    446	type DSCRM_DSC_OPP_PIPE_SOURCE
    447
    448
    449struct dcn20_dsc_registers {
    450	uint32_t DSC_TOP_CONTROL;
    451	uint32_t DSC_DEBUG_CONTROL;
    452	uint32_t DSCC_CONFIG0;
    453	uint32_t DSCC_CONFIG1;
    454	uint32_t DSCC_STATUS;
    455	uint32_t DSCC_INTERRUPT_CONTROL_STATUS;
    456	uint32_t DSCC_PPS_CONFIG0;
    457	uint32_t DSCC_PPS_CONFIG1;
    458	uint32_t DSCC_PPS_CONFIG2;
    459	uint32_t DSCC_PPS_CONFIG3;
    460	uint32_t DSCC_PPS_CONFIG4;
    461	uint32_t DSCC_PPS_CONFIG5;
    462	uint32_t DSCC_PPS_CONFIG6;
    463	uint32_t DSCC_PPS_CONFIG7;
    464	uint32_t DSCC_PPS_CONFIG8;
    465	uint32_t DSCC_PPS_CONFIG9;
    466	uint32_t DSCC_PPS_CONFIG10;
    467	uint32_t DSCC_PPS_CONFIG11;
    468	uint32_t DSCC_PPS_CONFIG12;
    469	uint32_t DSCC_PPS_CONFIG13;
    470	uint32_t DSCC_PPS_CONFIG14;
    471	uint32_t DSCC_PPS_CONFIG15;
    472	uint32_t DSCC_PPS_CONFIG16;
    473	uint32_t DSCC_PPS_CONFIG17;
    474	uint32_t DSCC_PPS_CONFIG18;
    475	uint32_t DSCC_PPS_CONFIG19;
    476	uint32_t DSCC_PPS_CONFIG20;
    477	uint32_t DSCC_PPS_CONFIG21;
    478	uint32_t DSCC_PPS_CONFIG22;
    479	uint32_t DSCC_MEM_POWER_CONTROL;
    480	uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;
    481	uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;
    482	uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;
    483	uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;
    484	uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;
    485	uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;
    486	uint32_t DSCC_MAX_ABS_ERROR0;
    487	uint32_t DSCC_MAX_ABS_ERROR1;
    488	uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL;
    489	uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL;
    490	uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL;
    491	uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL;
    492	uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL;
    493	uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
    494	uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
    495	uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
    496	uint32_t DSCCIF_CONFIG0;
    497	uint32_t DSCCIF_CONFIG1;
    498	uint32_t DSCRM_DSC_FORWARD_CONFIG;
    499};
    500
    501
    502struct dcn20_dsc_shift {
    503	DSC_FIELD_LIST_DCN20(uint8_t);
    504};
    505
    506struct dcn20_dsc_mask {
    507	DSC_FIELD_LIST_DCN20(uint32_t);
    508};
    509
    510/* DSCCIF_CONFIG.INPUT_PIXEL_FORMAT values */
    511enum dsc_pixel_format {
    512	DSC_PIXFMT_RGB,
    513	DSC_PIXFMT_YCBCR444,
    514	DSC_PIXFMT_SIMPLE_YCBCR422,
    515	DSC_PIXFMT_NATIVE_YCBCR422,
    516	DSC_PIXFMT_NATIVE_YCBCR420,
    517	DSC_PIXFMT_UNKNOWN
    518};
    519
    520struct dsc_reg_values {
    521	/* PPS registers */
    522	struct drm_dsc_config pps;
    523
    524	/* Additional registers */
    525	uint32_t dsc_clock_enable;
    526	uint32_t dsc_clock_gating_disable;
    527	uint32_t underflow_recovery_en;
    528	uint32_t underflow_occurred_int_en;
    529	uint32_t underflow_occurred_status;
    530	enum dsc_pixel_format pixel_format;
    531	uint32_t ich_reset_at_eol;
    532	uint32_t alternate_ich_encoding_en;
    533	uint32_t num_slices_h;
    534	uint32_t num_slices_v;
    535	uint32_t rc_buffer_model_size;
    536	uint32_t disable_ich;
    537	uint32_t bpp_x32;
    538	uint32_t dsc_dbg_en;
    539	uint32_t rc_buffer_model_overflow_int_en[4];
    540};
    541
    542struct dcn20_dsc {
    543	struct display_stream_compressor base;
    544	const struct dcn20_dsc_registers *dsc_regs;
    545	const struct dcn20_dsc_shift *dsc_shift;
    546	const struct dcn20_dsc_mask *dsc_mask;
    547
    548	struct dsc_reg_values reg_vals;
    549
    550	int max_image_width;
    551};
    552
    553
    554void dsc2_construct(struct dcn20_dsc *dsc,
    555		struct dc_context *ctx,
    556		int inst,
    557		const struct dcn20_dsc_registers *dsc_regs,
    558		const struct dcn20_dsc_shift *dsc_shift,
    559		const struct dcn20_dsc_mask *dsc_mask);
    560
    561#endif
    562