cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn201_link_encoder.c (7247B)


      1/*
      2 * Copyright 2012-15 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "reg_helper.h"
     27
     28#include "core_types.h"
     29#include "link_encoder.h"
     30#include "dcn201_link_encoder.h"
     31#include "stream_encoder.h"
     32#include "i2caux_interface.h"
     33#include "dc_bios_types.h"
     34
     35#include "gpio_service_interface.h"
     36
     37#define CTX \
     38	enc10->base.ctx
     39
     40#define DC_LOGGER \
     41	enc10->base.ctx->logger
     42
     43#define REG(reg)\
     44	(enc10->link_regs->reg)
     45
     46#undef FN
     47#define FN(reg_name, field_name) \
     48	enc10->link_shift->field_name, enc10->link_mask->field_name
     49
     50#define IND_REG(index) \
     51	(enc10->link_regs->index)
     52
     53static void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,
     54						 struct dc_link_settings *link_settings)
     55{
     56	uint32_t value1, value2;
     57	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
     58
     59	dcn10_link_encoder_get_max_link_cap(enc, link_settings);
     60	REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,
     61		 RDPCS_PHY_DPALT_DP4, &value2);
     62	/*limit to combo_phy*/
     63	if (enc->usbc_combo_phy) {
     64		if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO)
     65			link_settings->lane_count = LANE_COUNT_TWO;
     66	}
     67}
     68
     69static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
     70{
     71	uint32_t value;
     72	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
     73
     74	REG_GET(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value);
     75
     76	// if value == 1 alt mode is disabled, otherwise it is enabled
     77	return !value;
     78}
     79
     80static const struct link_encoder_funcs dcn201_link_enc_funcs = {
     81	.read_state = link_enc2_read_state,
     82	.validate_output_with_stream =
     83		dcn10_link_encoder_validate_output_with_stream,
     84	.hw_init = enc2_hw_init,
     85	.setup = dcn10_link_encoder_setup,
     86	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
     87	.enable_dp_output = dcn10_link_encoder_enable_dp_output,
     88	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
     89	.disable_output = dcn10_link_encoder_disable_output,
     90	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
     91	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
     92	.update_mst_stream_allocation_table =
     93		dcn10_link_encoder_update_mst_stream_allocation_table,
     94	.psr_program_dp_dphy_fast_training =
     95			dcn10_psr_program_dp_dphy_fast_training,
     96	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
     97	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
     98	.enable_hpd = dcn10_link_encoder_enable_hpd,
     99	.disable_hpd = dcn10_link_encoder_disable_hpd,
    100	.is_dig_enabled = dcn10_is_dig_enabled,
    101	.destroy = dcn10_link_encoder_destroy,
    102	.fec_set_enable = enc2_fec_set_enable,
    103	.fec_set_ready = enc2_fec_set_ready,
    104	.get_dig_frontend = dcn10_get_dig_frontend,
    105	.fec_is_active = enc2_fec_is_active,
    106	.is_in_alt_mode = dcn201_link_encoder_is_in_alt_mode,
    107	.get_max_link_cap = dcn201_link_encoder_get_max_link_cap,
    108};
    109
    110void dcn201_link_encoder_construct(
    111	struct dcn20_link_encoder *enc20,
    112	const struct encoder_init_data *init_data,
    113	const struct encoder_feature_support *enc_features,
    114	const struct dcn10_link_enc_registers *link_regs,
    115	const struct dcn10_link_enc_aux_registers *aux_regs,
    116	const struct dcn10_link_enc_hpd_registers *hpd_regs,
    117	const struct dcn10_link_enc_shift *link_shift,
    118	const struct dcn10_link_enc_mask *link_mask)
    119{
    120	struct bp_encoder_cap_info bp_cap_info = {0};
    121	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
    122	enum bp_result result = BP_RESULT_OK;
    123	struct dcn10_link_encoder *enc10 = &enc20->enc10;
    124
    125	enc10->base.funcs = &dcn201_link_enc_funcs;
    126	enc10->base.ctx = init_data->ctx;
    127	enc10->base.id = init_data->encoder;
    128
    129	enc10->base.hpd_source = init_data->hpd_source;
    130	enc10->base.connector = init_data->connector;
    131
    132	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
    133
    134	enc10->base.features = *enc_features;
    135
    136	enc10->base.transmitter = init_data->transmitter;
    137
    138	/* set the flag to indicate whether driver poll the I2C data pin
    139	 * while doing the DP sink detect
    140	 */
    141
    142	/* if (dal_adapter_service_is_feature_supported(as,
    143	 * FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
    144	 * enc10->base.features.flags.bits.
    145	 * DP_SINK_DETECT_POLL_DATA_PIN = true;
    146	 */
    147
    148	enc10->base.output_signals =
    149		SIGNAL_TYPE_DVI_SINGLE_LINK |
    150		SIGNAL_TYPE_DVI_DUAL_LINK |
    151		SIGNAL_TYPE_LVDS |
    152		SIGNAL_TYPE_DISPLAY_PORT |
    153		SIGNAL_TYPE_DISPLAY_PORT_MST |
    154		SIGNAL_TYPE_EDP |
    155		SIGNAL_TYPE_HDMI_TYPE_A;
    156
    157	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
    158	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
    159	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
    160	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
    161	 * Prefer DIG assignment is decided by board design.
    162	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
    163	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
    164	 * By this, adding DIGG should not hurt DCE 8.0.
    165	 * This will let DCE 8.1 share DCE 8.0 as much as possible
    166	 */
    167
    168	enc10->link_regs = link_regs;
    169	enc10->aux_regs = aux_regs;
    170	enc10->hpd_regs = hpd_regs;
    171	enc10->link_shift = link_shift;
    172	enc10->link_mask = link_mask;
    173
    174	switch (enc10->base.transmitter) {
    175	case TRANSMITTER_UNIPHY_A:
    176		enc10->base.preferred_engine = ENGINE_ID_DIGA;
    177	break;
    178	case TRANSMITTER_UNIPHY_B:
    179		enc10->base.preferred_engine = ENGINE_ID_DIGB;
    180	break;
    181	default:
    182		ASSERT_CRITICAL(false);
    183		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
    184	}
    185
    186	/* default to one to mirror Windows behavior */
    187	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
    188
    189	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
    190						enc10->base.id, &bp_cap_info);
    191
    192	/* Override features with DCE-specific values */
    193	if (result == BP_RESULT_OK) {
    194		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
    195				bp_cap_info.DP_HBR2_EN;
    196		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
    197				bp_cap_info.DP_HBR3_EN;
    198		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
    199		enc10->base.features.flags.bits.DP_IS_USB_C =
    200				bp_cap_info.DP_IS_USB_C;
    201	} else {
    202		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
    203				__func__,
    204				result);
    205	}
    206	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
    207		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
    208	}
    209}