cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dcn30_dwb.h (46789B)


      1/* Copyright 2020 Advanced Micro Devices, Inc.
      2 *
      3 * Permission is hereby granted, free of charge, to any person obtaining a
      4 * copy of this software and associated documentation files (the "Software"),
      5 * to deal in the Software without restriction, including without limitation
      6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      7 * and/or sell copies of the Software, and to permit persons to whom the
      8 * Software is furnished to do so, subject to the following conditions:
      9 *
     10 * The above copyright notice and this permission notice shall be included in
     11 * all copies or substantial portions of the Software.
     12 *
     13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     19 * OTHER DEALINGS IN THE SOFTWARE.
     20 *
     21 * Authors: AMD
     22 *
     23 */
     24#ifndef __DC_DWBC_DCN30_H__
     25#define __DC_DWBC_DCN30_H__
     26
     27#define TO_DCN30_DWBC(dwbc_base) \
     28	container_of(dwbc_base, struct dcn30_dwbc, base)
     29
     30/* DCN */
     31#define BASE_INNER(seg) \
     32	DCE_BASE__INST0_SEG ## seg
     33
     34#define BASE(seg) \
     35	BASE_INNER(seg)
     36
     37#define SF_DWB(reg_name, block, id, field_name, post_fix)\
     38	.field_name = block ## id ## _ ## reg_name ## __ ## field_name ## post_fix
     39
     40 /* set field name */
     41#define SF_DWB2(reg_name, block, id, field_name, post_fix)\
     42	.field_name = reg_name ## __ ## field_name ## post_fix
     43
     44
     45#define DWBC_COMMON_REG_LIST_DCN30(inst) \
     46	SR(DWB_ENABLE_CLK_CTRL),\
     47	SR(DWB_MEM_PWR_CTRL),\
     48	SR(FC_MODE_CTRL),\
     49	SR(FC_FLOW_CTRL),\
     50	SR(FC_WINDOW_START),\
     51	SR(FC_WINDOW_SIZE),\
     52	SR(FC_SOURCE_SIZE),\
     53	SR(DWB_UPDATE_CTRL),\
     54	SR(DWB_CRC_CTRL),\
     55	SR(DWB_CRC_MASK_R_G),\
     56	SR(DWB_CRC_MASK_B_A),\
     57	SR(DWB_CRC_VAL_R_G),\
     58	SR(DWB_CRC_VAL_B_A),\
     59	SR(DWB_OUT_CTRL),\
     60	SR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN),\
     61	SR(DWB_MMHUBBUB_BACKPRESSURE_CNT),\
     62	SR(DWB_HOST_READ_CONTROL),\
     63	SR(DWB_SOFT_RESET),\
     64	SR(DWB_HDR_MULT_COEF),\
     65	SR(DWB_GAMUT_REMAP_MODE),\
     66	SR(DWB_GAMUT_REMAP_COEF_FORMAT),\
     67	SR(DWB_GAMUT_REMAPA_C11_C12),\
     68	SR(DWB_GAMUT_REMAPA_C13_C14),\
     69	SR(DWB_GAMUT_REMAPA_C21_C22),\
     70	SR(DWB_GAMUT_REMAPA_C23_C24),\
     71	SR(DWB_GAMUT_REMAPA_C31_C32),\
     72	SR(DWB_GAMUT_REMAPA_C33_C34),\
     73	SR(DWB_GAMUT_REMAPB_C11_C12),\
     74	SR(DWB_GAMUT_REMAPB_C13_C14),\
     75	SR(DWB_GAMUT_REMAPB_C21_C22),\
     76	SR(DWB_GAMUT_REMAPB_C23_C24),\
     77	SR(DWB_GAMUT_REMAPB_C31_C32),\
     78	SR(DWB_GAMUT_REMAPB_C33_C34),\
     79	SR(DWB_OGAM_CONTROL),\
     80	SR(DWB_OGAM_LUT_INDEX),\
     81	SR(DWB_OGAM_LUT_DATA),\
     82	SR(DWB_OGAM_LUT_CONTROL),\
     83	SR(DWB_OGAM_RAMA_START_CNTL_B),\
     84	SR(DWB_OGAM_RAMA_START_CNTL_G),\
     85	SR(DWB_OGAM_RAMA_START_CNTL_R),\
     86	SR(DWB_OGAM_RAMA_START_BASE_CNTL_B),\
     87	SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B),\
     88	SR(DWB_OGAM_RAMA_START_BASE_CNTL_G),\
     89	SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G),\
     90	SR(DWB_OGAM_RAMA_START_BASE_CNTL_R),\
     91	SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R),\
     92	SR(DWB_OGAM_RAMA_END_CNTL1_B),\
     93	SR(DWB_OGAM_RAMA_END_CNTL2_B),\
     94	SR(DWB_OGAM_RAMA_END_CNTL1_G),\
     95	SR(DWB_OGAM_RAMA_END_CNTL2_G),\
     96	SR(DWB_OGAM_RAMA_END_CNTL1_R),\
     97	SR(DWB_OGAM_RAMA_END_CNTL2_R),\
     98	SR(DWB_OGAM_RAMA_OFFSET_B),\
     99	SR(DWB_OGAM_RAMA_OFFSET_G),\
    100	SR(DWB_OGAM_RAMA_OFFSET_R),\
    101	SR(DWB_OGAM_RAMA_REGION_0_1),\
    102	SR(DWB_OGAM_RAMA_REGION_2_3),\
    103	SR(DWB_OGAM_RAMA_REGION_4_5),\
    104	SR(DWB_OGAM_RAMA_REGION_6_7),\
    105	SR(DWB_OGAM_RAMA_REGION_8_9),\
    106	SR(DWB_OGAM_RAMA_REGION_10_11),\
    107	SR(DWB_OGAM_RAMA_REGION_12_13),\
    108	SR(DWB_OGAM_RAMA_REGION_14_15),\
    109	SR(DWB_OGAM_RAMA_REGION_16_17),\
    110	SR(DWB_OGAM_RAMA_REGION_18_19),\
    111	SR(DWB_OGAM_RAMA_REGION_20_21),\
    112	SR(DWB_OGAM_RAMA_REGION_22_23),\
    113	SR(DWB_OGAM_RAMA_REGION_24_25),\
    114	SR(DWB_OGAM_RAMA_REGION_26_27),\
    115	SR(DWB_OGAM_RAMA_REGION_28_29),\
    116	SR(DWB_OGAM_RAMA_REGION_30_31),\
    117	SR(DWB_OGAM_RAMA_REGION_32_33),\
    118	SR(DWB_OGAM_RAMB_START_CNTL_B),\
    119	SR(DWB_OGAM_RAMB_START_CNTL_G),\
    120	SR(DWB_OGAM_RAMB_START_CNTL_R),\
    121	SR(DWB_OGAM_RAMB_START_BASE_CNTL_B),\
    122	SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B),\
    123	SR(DWB_OGAM_RAMB_START_BASE_CNTL_G),\
    124	SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G),\
    125	SR(DWB_OGAM_RAMB_START_BASE_CNTL_R),\
    126	SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R),\
    127	SR(DWB_OGAM_RAMB_END_CNTL1_B),\
    128	SR(DWB_OGAM_RAMB_END_CNTL2_B),\
    129	SR(DWB_OGAM_RAMB_END_CNTL1_G),\
    130	SR(DWB_OGAM_RAMB_END_CNTL2_G),\
    131	SR(DWB_OGAM_RAMB_END_CNTL1_R),\
    132	SR(DWB_OGAM_RAMB_END_CNTL2_R),\
    133	SR(DWB_OGAM_RAMB_OFFSET_B),\
    134	SR(DWB_OGAM_RAMB_OFFSET_G),\
    135	SR(DWB_OGAM_RAMB_OFFSET_R),\
    136	SR(DWB_OGAM_RAMB_REGION_0_1),\
    137	SR(DWB_OGAM_RAMB_REGION_2_3),\
    138	SR(DWB_OGAM_RAMB_REGION_4_5),\
    139	SR(DWB_OGAM_RAMB_REGION_6_7),\
    140	SR(DWB_OGAM_RAMB_REGION_8_9),\
    141	SR(DWB_OGAM_RAMB_REGION_10_11),\
    142	SR(DWB_OGAM_RAMB_REGION_12_13),\
    143	SR(DWB_OGAM_RAMB_REGION_14_15),\
    144	SR(DWB_OGAM_RAMB_REGION_16_17),\
    145	SR(DWB_OGAM_RAMB_REGION_18_19),\
    146	SR(DWB_OGAM_RAMB_REGION_20_21),\
    147	SR(DWB_OGAM_RAMB_REGION_22_23),\
    148	SR(DWB_OGAM_RAMB_REGION_24_25),\
    149	SR(DWB_OGAM_RAMB_REGION_26_27),\
    150	SR(DWB_OGAM_RAMB_REGION_28_29),\
    151	SR(DWB_OGAM_RAMB_REGION_30_31),\
    152	SR(DWB_OGAM_RAMB_REGION_32_33)
    153
    154
    155#define DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \
    156	SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_ENABLE, mask_sh),\
    157	SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_R_DWB_GATE_DIS, mask_sh),\
    158	SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_G_DWB_GATE_DIS, mask_sh),\
    159	SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_TEST_CLK_SEL, mask_sh),\
    160	SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_FORCE, mask_sh),\
    161	SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_DIS, mask_sh),\
    162	SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_STATE, mask_sh),\
    163	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN, mask_sh),\
    164	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_RATE, mask_sh),\
    165	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_WINDOW_CROP_EN, mask_sh),\
    166	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_EYE_SELECTION, mask_sh),\
    167	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_STEREO_EYE_POLARITY, mask_sh),\
    168	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_NEW_CONTENT, mask_sh),\
    169	SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
    170	SF_DWB2(FC_FLOW_CTRL, DWB_TOP, 0, FC_FIRST_PIXEL_DELAY_COUNT, mask_sh),\
    171	SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_X, mask_sh),\
    172	SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_Y, mask_sh),\
    173	SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_WIDTH, mask_sh),\
    174	SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_HEIGHT, mask_sh),\
    175	SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_WIDTH, mask_sh),\
    176	SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_HEIGHT, mask_sh),\
    177	SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_LOCK, mask_sh),\
    178	SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_PENDING, mask_sh),\
    179	SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_EN, mask_sh),\
    180	SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_CONT_EN, mask_sh),\
    181	SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_SRC_SEL, mask_sh),\
    182	SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_RED_MASK, mask_sh),\
    183	SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_GREEN_MASK, mask_sh),\
    184	SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_BLUE_MASK, mask_sh),\
    185	SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_A_MASK, mask_sh),\
    186	SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_RED, mask_sh),\
    187	SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_GREEN, mask_sh),\
    188	SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_BLUE, mask_sh),\
    189	SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_A, mask_sh),\
    190	SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_FORMAT, mask_sh),\
    191	SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_DENORM, mask_sh),\
    192	SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MAX, mask_sh),\
    193	SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MIN, mask_sh),\
    194	SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, DWB_TOP, 0, DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, mask_sh),\
    195	SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT, DWB_TOP, 0, DWB_MMHUBBUB_MAX_BACKPRESSURE, mask_sh),\
    196	SF_DWB2(DWB_HOST_READ_CONTROL, DWB_TOP, 0, DWB_HOST_READ_RATE_CONTROL, mask_sh),\
    197	SF_DWB2(DWB_SOFT_RESET, DWB_TOP, 0, DWB_SOFT_RESET, mask_sh),\
    198	SF_DWB2(DWB_HDR_MULT_COEF, DWBCP, 0, DWB_HDR_MULT_COEF, mask_sh),\
    199	SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE, mask_sh),\
    200	SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
    201	SF_DWB2(DWB_GAMUT_REMAP_COEF_FORMAT, DWBCP, 0, DWB_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
    202	SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C11, mask_sh),\
    203	SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C12, mask_sh),\
    204	SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C13, mask_sh),\
    205	SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C14, mask_sh),\
    206	SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C21, mask_sh),\
    207	SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C22, mask_sh),\
    208	SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C23, mask_sh),\
    209	SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C24, mask_sh),\
    210	SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C31, mask_sh),\
    211	SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C32, mask_sh),\
    212	SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C33, mask_sh),\
    213	SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C34, mask_sh),\
    214	SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C11, mask_sh),\
    215	SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C12, mask_sh),\
    216	SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C13, mask_sh),\
    217	SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C14, mask_sh),\
    218	SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C21, mask_sh),\
    219	SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C22, mask_sh),\
    220	SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C23, mask_sh),\
    221	SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C24, mask_sh),\
    222	SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C31, mask_sh),\
    223	SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C32, mask_sh),\
    224	SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C33, mask_sh),\
    225	SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C34, mask_sh),\
    226	SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE, mask_sh),\
    227	SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT, mask_sh),\
    228	SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_PWL_DISABLE, mask_sh),\
    229	SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE_CURRENT, mask_sh),\
    230	SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT_CURRENT, mask_sh),\
    231	SF_DWB2(DWB_OGAM_LUT_INDEX, DWBCP, 0, DWB_OGAM_LUT_INDEX, mask_sh),\
    232	SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\
    233	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
    234	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
    235	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_DBG, mask_sh),\
    236	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\
    237	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\
    238	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
    239	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
    240	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_G, mask_sh),\
    241	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh),\
    242	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_R, mask_sh),\
    243	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh),\
    244	SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
    245	SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
    246	SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_G, mask_sh),\
    247	SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh),\
    248	SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_R, mask_sh),\
    249	SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh),\
    250	SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
    251	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
    252	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
    253	SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh),\
    254	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_G, mask_sh),\
    255	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh),\
    256	SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh),\
    257	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_R, mask_sh),\
    258	SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh),\
    259	SF_DWB2(DWB_OGAM_RAMA_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_B, mask_sh),\
    260	SF_DWB2(DWB_OGAM_RAMA_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_G, mask_sh),\
    261	SF_DWB2(DWB_OGAM_RAMA_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_R, mask_sh),\
    262	SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
    263	SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
    264	SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
    265	SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
    266	SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh),\
    267	SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh),\
    268	SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh),\
    269	SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh),\
    270	SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh),\
    271	SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh),\
    272	SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh),\
    273	SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh),\
    274	SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh),\
    275	SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh),\
    276	SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh),\
    277	SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh),\
    278	SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh),\
    279	SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh),\
    280	SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh),\
    281	SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh),\
    282	SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh),\
    283	SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh),\
    284	SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh),\
    285	SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh),\
    286	SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh),\
    287	SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh),\
    288	SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh),\
    289	SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh),\
    290	SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh),\
    291	SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh),\
    292	SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh),\
    293	SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh),\
    294	SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh),\
    295	SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh),\
    296	SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh),\
    297	SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh),\
    298	SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh),\
    299	SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh),\
    300	SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh),\
    301	SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh),\
    302	SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh),\
    303	SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh),\
    304	SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh),\
    305	SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh),\
    306	SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh),\
    307	SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh),\
    308	SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh),\
    309	SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh),\
    310	SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh),\
    311	SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh),\
    312	SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh),\
    313	SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh),\
    314	SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh),\
    315	SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh),\
    316	SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh),\
    317	SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh),\
    318	SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh),\
    319	SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh),\
    320	SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh),\
    321	SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh),\
    322	SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh),\
    323	SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh),\
    324	SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh),\
    325	SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh),\
    326	SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh),\
    327	SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh),\
    328	SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh),\
    329	SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh),\
    330	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
    331	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
    332	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_G, mask_sh),\
    333	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh),\
    334	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_R, mask_sh),\
    335	SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh),\
    336	SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_B, mask_sh),\
    337	SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh),\
    338	SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_G, mask_sh),\
    339	SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh),\
    340	SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_R, mask_sh),\
    341	SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh),\
    342	SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
    343	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
    344	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
    345	SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh),\
    346	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_G, mask_sh),\
    347	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh),\
    348	SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh),\
    349	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_R, mask_sh),\
    350	SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh),\
    351	SF_DWB2(DWB_OGAM_RAMB_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_B, mask_sh),\
    352	SF_DWB2(DWB_OGAM_RAMB_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_G, mask_sh),\
    353	SF_DWB2(DWB_OGAM_RAMB_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_R, mask_sh),\
    354	SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
    355	SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
    356	SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
    357	SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
    358	SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh),\
    359	SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh),\
    360	SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh),\
    361	SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh),\
    362	SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh),\
    363	SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh),\
    364	SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh),\
    365	SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh),\
    366	SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh),\
    367	SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh),\
    368	SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh),\
    369	SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh),\
    370	SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh),\
    371	SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh),\
    372	SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh),\
    373	SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh),\
    374	SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh),\
    375	SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh),\
    376	SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh),\
    377	SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh),\
    378	SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh),\
    379	SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh),\
    380	SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh),\
    381	SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh),\
    382	SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh),\
    383	SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh),\
    384	SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh),\
    385	SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh),\
    386	SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh),\
    387	SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh),\
    388	SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh),\
    389	SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh),\
    390	SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh),\
    391	SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh),\
    392	SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh),\
    393	SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh),\
    394	SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh),\
    395	SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh),\
    396	SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh),\
    397	SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh),\
    398	SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh),\
    399	SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh),\
    400	SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh),\
    401	SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh),\
    402	SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh),\
    403	SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh),\
    404	SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh),\
    405	SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh),\
    406	SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh),\
    407	SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh),\
    408	SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh),\
    409	SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh),\
    410	SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh),\
    411	SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh),\
    412	SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh),\
    413	SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh),\
    414	SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh),\
    415	SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh),\
    416	SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh),\
    417	SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh),\
    418	SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh),\
    419	SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh),\
    420	SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh),\
    421	SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh)
    422
    423
    424#define DWBC_REG_FIELD_LIST_DCN3_0(type) \
    425	type DWB_ENABLE;\
    426	type DISPCLK_R_DWB_GATE_DIS;\
    427	type DISPCLK_G_DWB_GATE_DIS;\
    428	type DWB_TEST_CLK_SEL;\
    429	type DWBSCL_LUT_MEM_PWR_FORCE;\
    430	type DWBSCL_LUT_MEM_PWR_DIS;\
    431	type DWBSCL_LUT_MEM_PWR_STATE;\
    432	type DWBSCL_LB_MEM_PWR_FORCE;\
    433	type DWBSCL_LB_MEM_PWR_DIS;\
    434	type DWBSCL_LB_MEM_PWR_STATE;\
    435	type DWB_OGAM_LUT_MEM_PWR_FORCE;\
    436	type DWB_OGAM_LUT_MEM_PWR_DIS;\
    437	type DWB_OGAM_LUT_MEM_PWR_STATE;\
    438	type FC_FRAME_CAPTURE_EN;\
    439	type FC_FRAME_CAPTURE_RATE;\
    440	type FC_WINDOW_CROP_EN;\
    441	type FC_EYE_SELECTION;\
    442	type FC_STEREO_EYE_POLARITY;\
    443	type FC_NEW_CONTENT;\
    444	type FC_FI_EN;\
    445	type FC_FI_PHASE;\
    446	type FC_FRAME_CAPTURE_EN_CURRENT;\
    447	type FC_FIRST_PIXEL_DELAY_COUNT;\
    448	type FC_WINDOW_START_X;\
    449	type FC_WINDOW_START_Y;\
    450	type FC_WINDOW_WIDTH;\
    451	type FC_WINDOW_HEIGHT;\
    452	type FC_SOURCE_WIDTH;\
    453	type FC_SOURCE_HEIGHT;\
    454	type DWB_UPDATE_LOCK;\
    455	type DWB_UPDATE_PENDING;\
    456	type DWB_CRC_EN;\
    457	type DWB_CRC_CONT_EN;\
    458	type DWB_CRC_SRC_SEL;\
    459	type DWB_CRC_RED_MASK;\
    460	type DWB_CRC_GREEN_MASK;\
    461	type DWB_CRC_BLUE_MASK;\
    462	type DWB_CRC_A_MASK;\
    463	type DWB_CRC_SIG_RED;\
    464	type DWB_CRC_SIG_GREEN;\
    465	type DWB_CRC_SIG_BLUE;\
    466	type DWB_CRC_SIG_A;\
    467	type OUT_FORMAT;\
    468	type OUT_DENORM;\
    469	type OUT_MAX;\
    470	type OUT_MIN;\
    471	type DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;\
    472	type DWB_MMHUBBUB_MAX_BACKPRESSURE;\
    473	type DWB_HOST_READ_RATE_CONTROL;\
    474	type DWBSCL_DATA_OVERFLOW_FLAG;\
    475	type DWBSCL_DATA_OVERFLOW_ACK;\
    476	type DWBSCL_DATA_OVERFLOW_MASK;\
    477	type DWBSCL_DATA_OVERFLOW_INT_STATUS;\
    478	type DWBSCL_DATA_OVERFLOW_INT_TYPE;\
    479	type DWBSCL_DATA_OVERFLOW_TYPE;\
    480	type DWBSCL_DATA_OVERFLOW_OUT_X_CNT;\
    481	type DWBSCL_DATA_OVERFLOW_OUT_Y_CNT;\
    482	type DWB_SOFT_RESET;\
    483	type DWBSCL_COEF_RAM_TAP_PAIR_IDX;\
    484	type DWBSCL_COEF_RAM_PHASE;\
    485	type DWBSCL_COEF_RAM_FILTER_TYPE;\
    486	type DWBSCL_COEF_RAM_SELECT_RD;\
    487	type DWBSCL_COEF_RAM_EVEN_TAP_COEF;\
    488	type DWBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
    489	type DWBSCL_COEF_RAM_ODD_TAP_COEF;\
    490	type DWBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
    491	type DWBSCL_MODE;\
    492	type DWBSCL_COEF_RAM_SELECT;\
    493	type DWBSCL_COEF_RAM_SELECT_CURRENT;\
    494	type DWBSCL_H_NUM_OF_TAPS;\
    495	type DWBSCL_V_NUM_OF_TAPS;\
    496	type DWBSCL_H_SCALE_RATIO;\
    497	type DWBSCL_H_INIT_FRAC;\
    498	type DWBSCL_H_INIT_INT;\
    499	type DWBSCL_V_SCALE_RATIO;\
    500	type DWBSCL_V_INIT_FRAC;\
    501	type DWBSCL_V_INIT_INT;\
    502	type DWBSCL_BOUNDARY_MODE;\
    503	type DWBSCL_BLACK_COLOR_RGB;\
    504	type DWBSCL_DEST_WIDTH;\
    505	type DWBSCL_DEST_HEIGHT;\
    506	type DWB_HDR_MULT_COEF;\
    507	type DWB_GAMUT_REMAP_MODE;\
    508	type DWB_GAMUT_REMAP_MODE_CURRENT;\
    509	type DWB_GAMUT_REMAP_COEF_FORMAT;\
    510	type DWB_GAMUT_REMAPA_C11;\
    511	type DWB_GAMUT_REMAPA_C12;\
    512	type DWB_GAMUT_REMAPA_C13;\
    513	type DWB_GAMUT_REMAPA_C14;\
    514	type DWB_GAMUT_REMAPA_C21;\
    515	type DWB_GAMUT_REMAPA_C22;\
    516	type DWB_GAMUT_REMAPA_C23;\
    517	type DWB_GAMUT_REMAPA_C24;\
    518	type DWB_GAMUT_REMAPA_C31;\
    519	type DWB_GAMUT_REMAPA_C32;\
    520	type DWB_GAMUT_REMAPA_C33;\
    521	type DWB_GAMUT_REMAPA_C34;\
    522	type DWB_GAMUT_REMAPB_C11;\
    523	type DWB_GAMUT_REMAPB_C12;\
    524	type DWB_GAMUT_REMAPB_C13;\
    525	type DWB_GAMUT_REMAPB_C14;\
    526	type DWB_GAMUT_REMAPB_C21;\
    527	type DWB_GAMUT_REMAPB_C22;\
    528	type DWB_GAMUT_REMAPB_C23;\
    529	type DWB_GAMUT_REMAPB_C24;\
    530	type DWB_GAMUT_REMAPB_C31;\
    531	type DWB_GAMUT_REMAPB_C32;\
    532	type DWB_GAMUT_REMAPB_C33;\
    533	type DWB_GAMUT_REMAPB_C34;\
    534	type DWB_OGAM_MODE;\
    535	type DWB_OGAM_SELECT;\
    536	type DWB_OGAM_PWL_DISABLE;\
    537	type DWB_OGAM_MODE_CURRENT;\
    538	type DWB_OGAM_SELECT_CURRENT;\
    539	type DWB_OGAM_LUT_INDEX;\
    540	type DWB_OGAM_LUT_DATA;\
    541	type DWB_OGAM_LUT_WRITE_COLOR_MASK;\
    542	type DWB_OGAM_LUT_READ_COLOR_SEL;\
    543	type DWB_OGAM_LUT_READ_DBG;\
    544	type DWB_OGAM_LUT_HOST_SEL;\
    545	type DWB_OGAM_LUT_CONFIG_MODE;\
    546	type DWB_OGAM_LUT_STATUS;\
    547	type DWB_OGAM_RAMA_EXP_REGION_START_B;\
    548	type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
    549	type DWB_OGAM_RAMA_EXP_REGION_START_G;\
    550	type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G;\
    551	type DWB_OGAM_RAMA_EXP_REGION_START_R;\
    552	type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R;\
    553	type DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;\
    554	type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;\
    555	type DWB_OGAM_RAMA_EXP_REGION_START_BASE_G;\
    556	type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G;\
    557	type DWB_OGAM_RAMA_EXP_REGION_START_BASE_R;\
    558	type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R;\
    559	type DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;\
    560	type DWB_OGAM_RAMA_EXP_REGION_END_B;\
    561	type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
    562	type DWB_OGAM_RAMA_EXP_REGION_END_BASE_G;\
    563	type DWB_OGAM_RAMA_EXP_REGION_END_G;\
    564	type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G;\
    565	type DWB_OGAM_RAMA_EXP_REGION_END_BASE_R;\
    566	type DWB_OGAM_RAMA_EXP_REGION_END_R;\
    567	type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R;\
    568	type DWB_OGAM_RAMA_OFFSET_B;\
    569	type DWB_OGAM_RAMA_OFFSET_G;\
    570	type DWB_OGAM_RAMA_OFFSET_R;\
    571	type DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
    572	type DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
    573	type DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
    574	type DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
    575	type DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET;\
    576	type DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS;\
    577	type DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET;\
    578	type DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS;\
    579	type DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET;\
    580	type DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS;\
    581	type DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET;\
    582	type DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS;\
    583	type DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET;\
    584	type DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS;\
    585	type DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET;\
    586	type DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS;\
    587	type DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET;\
    588	type DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS;\
    589	type DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET;\
    590	type DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS;\
    591	type DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET;\
    592	type DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS;\
    593	type DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET;\
    594	type DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS;\
    595	type DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET;\
    596	type DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS;\
    597	type DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET;\
    598	type DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS;\
    599	type DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET;\
    600	type DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS;\
    601	type DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET;\
    602	type DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS;\
    603	type DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET;\
    604	type DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS;\
    605	type DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET;\
    606	type DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS;\
    607	type DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET;\
    608	type DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS;\
    609	type DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET;\
    610	type DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS;\
    611	type DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET;\
    612	type DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS;\
    613	type DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET;\
    614	type DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS;\
    615	type DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET;\
    616	type DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS;\
    617	type DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET;\
    618	type DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS;\
    619	type DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET;\
    620	type DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS;\
    621	type DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET;\
    622	type DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS;\
    623	type DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET;\
    624	type DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS;\
    625	type DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET;\
    626	type DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS;\
    627	type DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET;\
    628	type DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS;\
    629	type DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET;\
    630	type DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS;\
    631	type DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET;\
    632	type DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS;\
    633	type DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET;\
    634	type DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS;\
    635	type DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET;\
    636	type DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS;\
    637	type DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET;\
    638	type DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS;\
    639	type DWB_OGAM_RAMB_EXP_REGION_START_B;\
    640	type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
    641	type DWB_OGAM_RAMB_EXP_REGION_START_G;\
    642	type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G;\
    643	type DWB_OGAM_RAMB_EXP_REGION_START_R;\
    644	type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R;\
    645	type DWB_OGAM_RAMB_EXP_REGION_START_BASE_B;\
    646	type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B;\
    647	type DWB_OGAM_RAMB_EXP_REGION_START_BASE_G;\
    648	type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G;\
    649	type DWB_OGAM_RAMB_EXP_REGION_START_BASE_R;\
    650	type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R;\
    651	type DWB_OGAM_RAMB_EXP_REGION_END_BASE_B;\
    652	type DWB_OGAM_RAMB_EXP_REGION_END_B;\
    653	type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
    654	type DWB_OGAM_RAMB_EXP_REGION_END_BASE_G;\
    655	type DWB_OGAM_RAMB_EXP_REGION_END_G;\
    656	type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G;\
    657	type DWB_OGAM_RAMB_EXP_REGION_END_BASE_R;\
    658	type DWB_OGAM_RAMB_EXP_REGION_END_R;\
    659	type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R;\
    660	type DWB_OGAM_RAMB_OFFSET_B;\
    661	type DWB_OGAM_RAMB_OFFSET_G;\
    662	type DWB_OGAM_RAMB_OFFSET_R;\
    663	type DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
    664	type DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
    665	type DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
    666	type DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
    667	type DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET;\
    668	type DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS;\
    669	type DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET;\
    670	type DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS;\
    671	type DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET;\
    672	type DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS;\
    673	type DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET;\
    674	type DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS;\
    675	type DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET;\
    676	type DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS;\
    677	type DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET;\
    678	type DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS;\
    679	type DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET;\
    680	type DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS;\
    681	type DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET;\
    682	type DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS;\
    683	type DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET;\
    684	type DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS;\
    685	type DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET;\
    686	type DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS;\
    687	type DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET;\
    688	type DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS;\
    689	type DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET;\
    690	type DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS;\
    691	type DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET;\
    692	type DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS;\
    693	type DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET;\
    694	type DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS;\
    695	type DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET;\
    696	type DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS;\
    697	type DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET;\
    698	type DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS;\
    699	type DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET;\
    700	type DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS;\
    701	type DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET;\
    702	type DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS;\
    703	type DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET;\
    704	type DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS;\
    705	type DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET;\
    706	type DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS;\
    707	type DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET;\
    708	type DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS;\
    709	type DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET;\
    710	type DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS;\
    711	type DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET;\
    712	type DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS;\
    713	type DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET;\
    714	type DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS;\
    715	type DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET;\
    716	type DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS;\
    717	type DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET;\
    718	type DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS;\
    719	type DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET;\
    720	type DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS;\
    721	type DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET;\
    722	type DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS;\
    723	type DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET;\
    724	type DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS;\
    725	type DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET;\
    726	type DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS;\
    727	type DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET;\
    728	type DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS;\
    729	type DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET;\
    730	type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS;
    731
    732struct dcn30_dwbc_registers {
    733	/* DCN3AG */
    734	/* DWB_TOP */
    735	uint32_t DWB_ENABLE_CLK_CTRL;
    736	uint32_t DWB_MEM_PWR_CTRL;
    737	uint32_t FC_MODE_CTRL;
    738	uint32_t FC_FLOW_CTRL;
    739	uint32_t FC_WINDOW_START;
    740	uint32_t FC_WINDOW_SIZE;
    741	uint32_t FC_SOURCE_SIZE;
    742	uint32_t DWB_UPDATE_CTRL;
    743	uint32_t DWB_CRC_CTRL;
    744	uint32_t DWB_CRC_MASK_R_G;
    745	uint32_t DWB_CRC_MASK_B_A;
    746	uint32_t DWB_CRC_VAL_R_G;
    747	uint32_t DWB_CRC_VAL_B_A;
    748	uint32_t DWB_OUT_CTRL;
    749	uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;
    750	uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;
    751	uint32_t DWB_HOST_READ_CONTROL;
    752	uint32_t DWB_SOFT_RESET;
    753
    754	/* DWBSCL */
    755	uint32_t DWBSCL_COEF_RAM_TAP_SELECT;
    756	uint32_t DWBSCL_COEF_RAM_TAP_DATA;
    757	uint32_t DWBSCL_MODE;
    758	uint32_t DWBSCL_TAP_CONTROL;
    759	uint32_t DWBSCL_HORZ_FILTER_SCALE_RATIO;
    760	uint32_t DWBSCL_HORZ_FILTER_INIT;
    761	uint32_t DWBSCL_VERT_FILTER_SCALE_RATIO;
    762	uint32_t DWBSCL_VERT_FILTER_INIT;
    763	uint32_t DWBSCL_BOUNDARY_CTRL;
    764	uint32_t DWBSCL_DEST_SIZE;
    765	uint32_t DWBSCL_OVERFLOW_STATUS;
    766	uint32_t DWBSCL_OVERFLOW_COUNTER;
    767
    768	/* DWBCP */
    769	uint32_t DWB_HDR_MULT_COEF;
    770	uint32_t DWB_GAMUT_REMAP_MODE;
    771	uint32_t DWB_GAMUT_REMAP_COEF_FORMAT;
    772	uint32_t DWB_GAMUT_REMAPA_C11_C12;
    773	uint32_t DWB_GAMUT_REMAPA_C13_C14;
    774	uint32_t DWB_GAMUT_REMAPA_C21_C22;
    775	uint32_t DWB_GAMUT_REMAPA_C23_C24;
    776	uint32_t DWB_GAMUT_REMAPA_C31_C32;
    777	uint32_t DWB_GAMUT_REMAPA_C33_C34;
    778	uint32_t DWB_GAMUT_REMAPB_C11_C12;
    779	uint32_t DWB_GAMUT_REMAPB_C13_C14;
    780	uint32_t DWB_GAMUT_REMAPB_C21_C22;
    781	uint32_t DWB_GAMUT_REMAPB_C23_C24;
    782	uint32_t DWB_GAMUT_REMAPB_C31_C32;
    783	uint32_t DWB_GAMUT_REMAPB_C33_C34;
    784	uint32_t DWB_OGAM_CONTROL;
    785	uint32_t DWB_OGAM_LUT_INDEX;
    786	uint32_t DWB_OGAM_LUT_DATA;
    787	uint32_t DWB_OGAM_LUT_CONTROL;
    788	uint32_t DWB_OGAM_RAMA_START_CNTL_B;
    789	uint32_t DWB_OGAM_RAMA_START_CNTL_G;
    790	uint32_t DWB_OGAM_RAMA_START_CNTL_R;
    791	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_B;
    792	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_B;
    793	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_G;
    794	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_G;
    795	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_R;
    796	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_R;
    797	uint32_t DWB_OGAM_RAMA_END_CNTL1_B;
    798	uint32_t DWB_OGAM_RAMA_END_CNTL2_B;
    799	uint32_t DWB_OGAM_RAMA_END_CNTL1_G;
    800	uint32_t DWB_OGAM_RAMA_END_CNTL2_G;
    801	uint32_t DWB_OGAM_RAMA_END_CNTL1_R;
    802	uint32_t DWB_OGAM_RAMA_END_CNTL2_R;
    803	uint32_t DWB_OGAM_RAMA_OFFSET_B;
    804	uint32_t DWB_OGAM_RAMA_OFFSET_G;
    805	uint32_t DWB_OGAM_RAMA_OFFSET_R;
    806	uint32_t DWB_OGAM_RAMA_REGION_0_1;
    807	uint32_t DWB_OGAM_RAMA_REGION_2_3;
    808	uint32_t DWB_OGAM_RAMA_REGION_4_5;
    809	uint32_t DWB_OGAM_RAMA_REGION_6_7;
    810	uint32_t DWB_OGAM_RAMA_REGION_8_9;
    811	uint32_t DWB_OGAM_RAMA_REGION_10_11;
    812	uint32_t DWB_OGAM_RAMA_REGION_12_13;
    813	uint32_t DWB_OGAM_RAMA_REGION_14_15;
    814	uint32_t DWB_OGAM_RAMA_REGION_16_17;
    815	uint32_t DWB_OGAM_RAMA_REGION_18_19;
    816	uint32_t DWB_OGAM_RAMA_REGION_20_21;
    817	uint32_t DWB_OGAM_RAMA_REGION_22_23;
    818	uint32_t DWB_OGAM_RAMA_REGION_24_25;
    819	uint32_t DWB_OGAM_RAMA_REGION_26_27;
    820	uint32_t DWB_OGAM_RAMA_REGION_28_29;
    821	uint32_t DWB_OGAM_RAMA_REGION_30_31;
    822	uint32_t DWB_OGAM_RAMA_REGION_32_33;
    823	uint32_t DWB_OGAM_RAMB_START_CNTL_B;
    824	uint32_t DWB_OGAM_RAMB_START_CNTL_G;
    825	uint32_t DWB_OGAM_RAMB_START_CNTL_R;
    826	uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_B;
    827	uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_B;
    828	uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_G;
    829	uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_G;
    830	uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_R;
    831	uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_R;
    832	uint32_t DWB_OGAM_RAMB_END_CNTL1_B;
    833	uint32_t DWB_OGAM_RAMB_END_CNTL2_B;
    834	uint32_t DWB_OGAM_RAMB_END_CNTL1_G;
    835	uint32_t DWB_OGAM_RAMB_END_CNTL2_G;
    836	uint32_t DWB_OGAM_RAMB_END_CNTL1_R;
    837	uint32_t DWB_OGAM_RAMB_END_CNTL2_R;
    838	uint32_t DWB_OGAM_RAMB_OFFSET_B;
    839	uint32_t DWB_OGAM_RAMB_OFFSET_G;
    840	uint32_t DWB_OGAM_RAMB_OFFSET_R;
    841	uint32_t DWB_OGAM_RAMB_REGION_0_1;
    842	uint32_t DWB_OGAM_RAMB_REGION_2_3;
    843	uint32_t DWB_OGAM_RAMB_REGION_4_5;
    844	uint32_t DWB_OGAM_RAMB_REGION_6_7;
    845	uint32_t DWB_OGAM_RAMB_REGION_8_9;
    846	uint32_t DWB_OGAM_RAMB_REGION_10_11;
    847	uint32_t DWB_OGAM_RAMB_REGION_12_13;
    848	uint32_t DWB_OGAM_RAMB_REGION_14_15;
    849	uint32_t DWB_OGAM_RAMB_REGION_16_17;
    850	uint32_t DWB_OGAM_RAMB_REGION_18_19;
    851	uint32_t DWB_OGAM_RAMB_REGION_20_21;
    852	uint32_t DWB_OGAM_RAMB_REGION_22_23;
    853	uint32_t DWB_OGAM_RAMB_REGION_24_25;
    854	uint32_t DWB_OGAM_RAMB_REGION_26_27;
    855	uint32_t DWB_OGAM_RAMB_REGION_28_29;
    856	uint32_t DWB_OGAM_RAMB_REGION_30_31;
    857	uint32_t DWB_OGAM_RAMB_REGION_32_33;
    858};
    859
    860/* Internal enums / structs */
    861enum dwbscl_coef_filter_type_sel {
    862	DWBSCL_COEF_RAM_FILTER_TYPE_VERT_RGB = 0,
    863	DWBSCL_COEF_RAM_FILTER_TYPE_HORZ_RGB = 1
    864};
    865
    866
    867struct dcn30_dwbc_mask {
    868	DWBC_REG_FIELD_LIST_DCN3_0(uint32_t);
    869};
    870
    871struct dcn30_dwbc_shift {
    872	DWBC_REG_FIELD_LIST_DCN3_0(uint8_t);
    873};
    874
    875struct dcn30_dwbc {
    876	struct dwbc base;
    877	const struct dcn30_dwbc_registers *dwbc_regs;
    878	const struct dcn30_dwbc_shift *dwbc_shift;
    879	const struct dcn30_dwbc_mask *dwbc_mask;
    880};
    881
    882void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
    883	struct dc_context *ctx,
    884	const struct dcn30_dwbc_registers *dwbc_regs,
    885	const struct dcn30_dwbc_shift *dwbc_shift,
    886	const struct dcn30_dwbc_mask *dwbc_mask,
    887	int inst);
    888
    889bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
    890
    891bool dwb3_disable(struct dwbc *dwbc);
    892
    893bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
    894
    895bool dwb3_is_enabled(struct dwbc *dwbc);
    896
    897void dwb3_set_stereo(struct dwbc *dwbc,
    898	struct dwb_stereo_params *stereo_params);
    899
    900void dwb3_set_new_content(struct dwbc *dwbc,
    901	bool is_new_content);
    902
    903void dwb3_config_fc(struct dwbc *dwbc,
    904	struct dc_dwb_params *params);
    905
    906void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
    907
    908void dwb3_program_hdr_mult(
    909	struct dwbc *dwbc,
    910	const struct dc_dwb_params *params);
    911
    912void dwb3_set_gamut_remap(
    913	struct dwbc *dwbc,
    914	const struct dc_dwb_params *params);
    915
    916bool dwb3_ogam_set_input_transfer_func(
    917	struct dwbc *dwbc,
    918	const struct dc_transfer_func *in_transfer_func_dwb_ogam);
    919
    920void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay);
    921#endif
    922
    923