cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn301_dio_link_encoder.c (6847B)


      1/*
      2 * Copyright 2020 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "reg_helper.h"
     27
     28#include "core_types.h"
     29#include "link_encoder.h"
     30#include "dcn301_dio_link_encoder.h"
     31#include "stream_encoder.h"
     32#include "i2caux_interface.h"
     33#include "dc_bios_types.h"
     34#include "gpio_service_interface.h"
     35
     36#define CTX \
     37	enc10->base.ctx
     38#define DC_LOGGER \
     39	enc10->base.ctx->logger
     40
     41#define REG(reg)\
     42	(enc10->link_regs->reg)
     43
     44#undef FN
     45#define FN(reg_name, field_name) \
     46	enc10->link_shift->field_name, enc10->link_mask->field_name
     47
     48#define IND_REG(index) \
     49	(enc10->link_regs->index)
     50
     51static const struct link_encoder_funcs dcn301_link_enc_funcs = {
     52	.read_state = link_enc2_read_state,
     53	.validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream,
     54	.hw_init = enc3_hw_init,
     55	.setup = dcn10_link_encoder_setup,
     56	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
     57	.enable_dp_output = dcn20_link_encoder_enable_dp_output,
     58	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
     59	.disable_output = dcn10_link_encoder_disable_output,
     60	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
     61	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
     62	.update_mst_stream_allocation_table = dcn10_link_encoder_update_mst_stream_allocation_table,
     63	.psr_program_dp_dphy_fast_training = dcn10_psr_program_dp_dphy_fast_training,
     64	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
     65	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
     66	.enable_hpd = dcn10_link_encoder_enable_hpd,
     67	.disable_hpd = dcn10_link_encoder_disable_hpd,
     68	.is_dig_enabled = dcn10_is_dig_enabled,
     69	.destroy = dcn10_link_encoder_destroy,
     70	.fec_set_enable = enc2_fec_set_enable,
     71	.fec_set_ready = enc2_fec_set_ready,
     72	.fec_is_active = enc2_fec_is_active,
     73	.get_dig_frontend = dcn10_get_dig_frontend,
     74	.get_dig_mode = dcn10_get_dig_mode,
     75	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
     76	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
     77};
     78
     79void dcn301_link_encoder_construct(
     80	struct dcn20_link_encoder *enc20,
     81	const struct encoder_init_data *init_data,
     82	const struct encoder_feature_support *enc_features,
     83	const struct dcn10_link_enc_registers *link_regs,
     84	const struct dcn10_link_enc_aux_registers *aux_regs,
     85	const struct dcn10_link_enc_hpd_registers *hpd_regs,
     86	const struct dcn10_link_enc_shift *link_shift,
     87	const struct dcn10_link_enc_mask *link_mask)
     88{
     89	struct bp_encoder_cap_info bp_cap_info = {0};
     90	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
     91	enum bp_result result = BP_RESULT_OK;
     92	struct dcn10_link_encoder *enc10 = &enc20->enc10;
     93
     94	enc10->base.funcs = &dcn301_link_enc_funcs;
     95	enc10->base.ctx = init_data->ctx;
     96	enc10->base.id = init_data->encoder;
     97
     98	enc10->base.hpd_source = init_data->hpd_source;
     99	enc10->base.connector = init_data->connector;
    100
    101	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
    102
    103	enc10->base.features = *enc_features;
    104
    105	enc10->base.transmitter = init_data->transmitter;
    106
    107	/* set the flag to indicate whether driver poll the I2C data pin
    108	 * while doing the DP sink detect
    109	 */
    110
    111/*	if (dal_adapter_service_is_feature_supported(as,
    112		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
    113		enc10->base.features.flags.bits.
    114			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
    115
    116	enc10->base.output_signals =
    117		SIGNAL_TYPE_DVI_SINGLE_LINK |
    118		SIGNAL_TYPE_DVI_DUAL_LINK |
    119		SIGNAL_TYPE_LVDS |
    120		SIGNAL_TYPE_DISPLAY_PORT |
    121		SIGNAL_TYPE_DISPLAY_PORT_MST |
    122		SIGNAL_TYPE_EDP |
    123		SIGNAL_TYPE_HDMI_TYPE_A;
    124
    125	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
    126	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
    127	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
    128	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
    129	 * Prefer DIG assignment is decided by board design.
    130	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
    131	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
    132	 * By this, adding DIGG should not hurt DCE 8.0.
    133	 * This will let DCE 8.1 share DCE 8.0 as much as possible
    134	 */
    135
    136	enc10->link_regs = link_regs;
    137	enc10->aux_regs = aux_regs;
    138	enc10->hpd_regs = hpd_regs;
    139	enc10->link_shift = link_shift;
    140	enc10->link_mask = link_mask;
    141
    142	switch (enc10->base.transmitter) {
    143	case TRANSMITTER_UNIPHY_A:
    144		enc10->base.preferred_engine = ENGINE_ID_DIGA;
    145	break;
    146	case TRANSMITTER_UNIPHY_B:
    147		enc10->base.preferred_engine = ENGINE_ID_DIGB;
    148	break;
    149	case TRANSMITTER_UNIPHY_C:
    150		enc10->base.preferred_engine = ENGINE_ID_DIGC;
    151	break;
    152	case TRANSMITTER_UNIPHY_D:
    153		enc10->base.preferred_engine = ENGINE_ID_DIGD;
    154	break;
    155	case TRANSMITTER_UNIPHY_E:
    156		enc10->base.preferred_engine = ENGINE_ID_DIGE;
    157	break;
    158	case TRANSMITTER_UNIPHY_F:
    159		enc10->base.preferred_engine = ENGINE_ID_DIGF;
    160	break;
    161	case TRANSMITTER_UNIPHY_G:
    162		enc10->base.preferred_engine = ENGINE_ID_DIGG;
    163	break;
    164	default:
    165		ASSERT_CRITICAL(false);
    166		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
    167	}
    168
    169	/* default to one to mirror Windows behavior */
    170	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
    171
    172	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
    173						enc10->base.id, &bp_cap_info);
    174
    175	/* Override features with DCE-specific values */
    176	if (result == BP_RESULT_OK) {
    177		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
    178				bp_cap_info.DP_HBR2_EN;
    179		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
    180				bp_cap_info.DP_HBR3_EN;
    181		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
    182		enc10->base.features.flags.bits.DP_IS_USB_C =
    183				bp_cap_info.DP_IS_USB_C;
    184	} else {
    185		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
    186				__func__,
    187				result);
    188	}
    189	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
    190		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
    191	}
    192}