cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn301_init.c (6736B)


      1/*
      2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "dce110/dce110_hw_sequencer.h"
     27#include "dcn10/dcn10_hw_sequencer.h"
     28#include "dcn20/dcn20_hwseq.h"
     29#include "dcn21/dcn21_hwseq.h"
     30#include "dcn30/dcn30_hwseq.h"
     31#include "dcn301_hwseq.h"
     32
     33#include "dcn301_init.h"
     34
     35static const struct hw_sequencer_funcs dcn301_funcs = {
     36	.program_gamut_remap = dcn10_program_gamut_remap,
     37	.init_hw = dcn10_init_hw,
     38	.power_down_on_boot = dcn10_power_down_on_boot,
     39	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
     40	.apply_ctx_for_surface = NULL,
     41	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
     42	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
     43	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
     44	.update_plane_addr = dcn20_update_plane_addr,
     45	.update_dchub = dcn10_update_dchub,
     46	.update_pending_status = dcn10_update_pending_status,
     47	.program_output_csc = dcn20_program_output_csc,
     48	.enable_accelerated_mode = dce110_enable_accelerated_mode,
     49	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
     50	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
     51	.update_info_frame = dcn30_update_info_frame,
     52	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
     53	.enable_stream = dcn20_enable_stream,
     54	.disable_stream = dce110_disable_stream,
     55	.unblank_stream = dcn20_unblank_stream,
     56#ifdef FREESYNC_POWER_OPTIMIZE
     57	.are_streams_coarse_grain_aligned = dcn20_are_streams_coarse_grain_aligned,
     58#endif
     59	.blank_stream = dce110_blank_stream,
     60	.enable_audio_stream = dce110_enable_audio_stream,
     61	.disable_audio_stream = dce110_disable_audio_stream,
     62	.disable_plane = dcn20_disable_plane,
     63	.pipe_control_lock = dcn20_pipe_control_lock,
     64	.interdependent_update_lock = dcn10_lock_all_pipes,
     65	.cursor_lock = dcn10_cursor_lock,
     66	.prepare_bandwidth = dcn20_prepare_bandwidth,
     67	.optimize_bandwidth = dcn20_optimize_bandwidth,
     68	.update_bandwidth = dcn20_update_bandwidth,
     69	.set_drr = dcn10_set_drr,
     70	.get_position = dcn10_get_position,
     71	.set_static_screen_control = dcn10_set_static_screen_control,
     72	.setup_stereo = dcn10_setup_stereo,
     73	.set_avmute = dcn30_set_avmute,
     74	.log_hw_state = dcn10_log_hw_state,
     75	.get_hw_state = dcn10_get_hw_state,
     76	.clear_status_bits = dcn10_clear_status_bits,
     77	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
     78	.edp_power_control = dce110_edp_power_control,
     79	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
     80	.set_cursor_position = dcn10_set_cursor_position,
     81	.set_cursor_attribute = dcn10_set_cursor_attribute,
     82	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
     83	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
     84	.set_clock = dcn10_set_clock,
     85	.get_clock = dcn10_get_clock,
     86	.program_triplebuffer = dcn20_program_triple_buffer,
     87	.enable_writeback = dcn30_enable_writeback,
     88	.disable_writeback = dcn30_disable_writeback,
     89	.update_writeback = dcn30_update_writeback,
     90	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
     91	.dmdata_status_done = dcn20_dmdata_status_done,
     92	.program_dmdata_engine = dcn30_program_dmdata_engine,
     93	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
     94	.init_sys_ctx = dcn20_init_sys_ctx,
     95	.init_vm_ctx = dcn20_init_vm_ctx,
     96	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
     97	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
     98	.calc_vupdate_position = dcn10_calc_vupdate_position,
     99	.set_backlight_level = dcn21_set_backlight_level,
    100	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
    101	.set_pipe = dcn21_set_pipe,
    102	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
    103	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
    104	.optimize_pwr_state = dcn21_optimize_pwr_state,
    105	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
    106	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
    107};
    108
    109static const struct hwseq_private_funcs dcn301_private_funcs = {
    110	.init_pipes = dcn10_init_pipes,
    111	.update_plane_addr = dcn20_update_plane_addr,
    112	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
    113	.update_mpcc = dcn20_update_mpcc,
    114	.set_input_transfer_func = dcn30_set_input_transfer_func,
    115	.set_output_transfer_func = dcn30_set_output_transfer_func,
    116	.power_down = dce110_power_down,
    117	.enable_display_power_gating = dcn10_dummy_display_power_gating,
    118	.blank_pixel_data = dcn20_blank_pixel_data,
    119	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
    120	.enable_stream_timing = dcn20_enable_stream_timing,
    121	.edp_backlight_control = dce110_edp_backlight_control,
    122	.disable_stream_gating = dcn20_disable_stream_gating,
    123	.enable_stream_gating = dcn20_enable_stream_gating,
    124	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
    125	.did_underflow_occur = dcn10_did_underflow_occur,
    126	.init_blank = dcn20_init_blank,
    127	.disable_vga = dcn20_disable_vga,
    128	.bios_golden_init = dcn10_bios_golden_init,
    129	.plane_atomic_disable = dcn20_plane_atomic_disable,
    130	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
    131	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
    132	.dpp_pg_control = dcn20_dpp_pg_control,
    133	.hubp_pg_control = dcn20_hubp_pg_control,
    134	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
    135	.update_odm = dcn20_update_odm,
    136	.dsc_pg_control = dcn20_dsc_pg_control,
    137	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
    138	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
    139	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
    140	.dccg_init = dcn20_dccg_init,
    141	.set_blend_lut = dcn30_set_blend_lut,
    142	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
    143};
    144
    145void dcn301_hw_sequencer_construct(struct dc *dc)
    146{
    147	dc->hwss = dcn301_funcs;
    148	dc->hwseq->funcs = dcn301_private_funcs;
    149}