dcn31_resource.h (4321B)
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef _DCN31_RESOURCE_H_ 27#define _DCN31_RESOURCE_H_ 28 29#include "core_types.h" 30 31#define TO_DCN31_RES_POOL(pool)\ 32 container_of(pool, struct dcn31_resource_pool, base) 33 34extern struct _vcs_dpi_ip_params_st dcn3_1_ip; 35extern struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc; 36 37struct dcn31_resource_pool { 38 struct resource_pool base; 39}; 40 41bool dcn31_validate_bandwidth(struct dc *dc, 42 struct dc_state *context, 43 bool fast_validate); 44void dcn31_calculate_wm_and_dlg( 45 struct dc *dc, struct dc_state *context, 46 display_e2e_pipe_params_st *pipes, 47 int pipe_cnt, 48 int vlevel); 49int dcn31_populate_dml_pipes_from_context( 50 struct dc *dc, struct dc_state *context, 51 display_e2e_pipe_params_st *pipes, 52 bool fast_validate); 53void 54dcn31_populate_dml_writeback_from_context(struct dc *dc, 55 struct resource_context *res_ctx, 56 display_e2e_pipe_params_st *pipes); 57void 58dcn31_set_mcif_arb_params(struct dc *dc, 59 struct dc_state *context, 60 display_e2e_pipe_params_st *pipes, 61 int pipe_cnt); 62void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); 63 64struct resource_pool *dcn31_create_resource_pool( 65 const struct dc_init_data *init_data, 66 struct dc *dc); 67 68/*temp: B0 specific before switch to dcn313 headers*/ 69#ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL 70#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 71#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 72#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 73#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 74 75//PHYPLLF_PIXCLK_RESYNC_CNTL 76#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 77#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 78#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 79#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 80#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 81#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 82#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 83#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 84#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L 85#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 86 87//PHYPLLG_PIXCLK_RESYNC_CNTL 88#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 89#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 90#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 91#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 92#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 93#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L 94#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L 95#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L 96#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L 97#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L 98#endif 99#endif /* _DCN31_RESOURCE_H_ */