cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dcn10_fpu.c (4989B)

      1// SPDX-License-Identifier: MIT
      2/*
      3 * Copyright 2021 Advanced Micro Devices, Inc.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be included in
     13 * all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     21 * OTHER DEALINGS IN THE SOFTWARE.
     22 *
     23 * Authors: AMD
     24 *
     25 */
     26
     27#include "dcn10/dcn10_resource.h"
     28
     29#include "dcn10_fpu.h"
     30
     31/**
     32 * DOC: DCN10 FPU manipulation Overview
     33 *
     34 * The DCN architecture relies on FPU operations, which require special
     35 * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
     36 * want to avoid spreading FPU access across multiple files. With this idea in
     37 * mind, this file aims to centralize DCN10 functions that require FPU access
     38 * in a single place. Code in this file follows the following code pattern:
     39 *
     40 * 1. Functions that use FPU operations should be isolated in static functions.
     41 * 2. The FPU functions should have the noinline attribute to ensure anything
     42 *    that deals with FP register is contained within this call.
     43 * 3. All function that needs to be accessed outside this file requires a
     44 *    public interface that not uses any FPU reference.
     45 * 4. Developers **must not** use DC_FP_START/END in this file, but they need
     46 *    to ensure that the caller invokes it before access any function available
     47 *    in this file. For this reason, public functions in this file must invoke
     48 *    dc_assert_fp_enabled();
     49 *
     50 * Let's expand a little bit more the idea in the code pattern. To fully
     51 * isolate FPU operations in a single place, we must avoid situations where
     52 * compilers spill FP values to registers due to FP enable in a specific C
     53 * file. Note that even if we isolate all FPU functions in a single file and
     54 * call its interface from other files, the compiler might enable the use of
     55 * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
     56 * responsibility to invoke DC_FP_START/END in the correct place. To highlight
     57 * situations where developers forgot to use the FP protection before calling
     58 * the DC FPU interface functions, we introduce a helper that checks if the
     59 * function is invoked under FP protection. If not, it will trigger a kernel
     60 * warning.
     61 */
     62
     63struct _vcs_dpi_ip_params_st dcn1_0_ip = {
     64	.rob_buffer_size_kbytes = 64,
     65	.det_buffer_size_kbytes = 164,
     66	.dpte_buffer_size_in_pte_reqs_luma = 42,
     67	.dpp_output_buffer_pixels = 2560,
     68	.opp_output_buffer_lines = 1,
     69	.pixel_chunk_size_kbytes = 8,
     70	.pte_enable = 1,
     71	.pte_chunk_size_kbytes = 2,
     72	.meta_chunk_size_kbytes = 2,
     73	.writeback_chunk_size_kbytes = 2,
     74	.line_buffer_size_bits = 589824,
     75	.max_line_buffer_lines = 12,
     76	.IsLineBufferBppFixed = 0,
     77	.LineBufferFixedBpp = -1,
     78	.writeback_luma_buffer_size_kbytes = 12,
     79	.writeback_chroma_buffer_size_kbytes = 8,
     80	.max_num_dpp = 4,
     81	.max_num_wb = 2,
     82	.max_dchub_pscl_bw_pix_per_clk = 4,
     83	.max_pscl_lb_bw_pix_per_clk = 2,
     84	.max_lb_vscl_bw_pix_per_clk = 4,
     85	.max_vscl_hscl_bw_pix_per_clk = 4,
     86	.max_hscl_ratio = 4,
     87	.max_vscl_ratio = 4,
     88	.hscl_mults = 4,
     89	.vscl_mults = 4,
     90	.max_hscl_taps = 8,
     91	.max_vscl_taps = 8,
     92	.dispclk_ramp_margin_percent = 1,
     93	.underscan_factor = 1.10,
     94	.min_vblank_lines = 14,
     95	.dppclk_delay_subtotal = 90,
     96	.dispclk_delay_subtotal = 42,
     97	.dcfclk_cstate_latency = 10,
     98	.max_inter_dcn_tile_repeaters = 8,
     99	.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
    100	.bug_forcing_LC_req_same_size_fixed = 0,
    101};
    102
    103struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
    104	.sr_exit_time_us = 9.0,
    105	.sr_enter_plus_exit_time_us = 11.0,
    106	.urgent_latency_us = 4.0,
    107	.writeback_latency_us = 12.0,
    108	.ideal_dram_bw_after_urgent_percent = 80.0,
    109	.max_request_size_bytes = 256,
    110	.downspread_percent = 0.5,
    111	.dram_page_open_time_ns = 50.0,
    112	.dram_rw_turnaround_time_ns = 17.5,
    113	.dram_return_buffer_per_channel_bytes = 8192,
    114	.round_trip_ping_latency_dcfclk_cycles = 128,
    115	.urgent_out_of_order_return_per_channel_bytes = 256,
    116	.channel_interleave_bytes = 256,
    117	.num_banks = 8,
    118	.num_chans = 2,
    119	.vmm_page_size_bytes = 4096,
    120	.dram_clock_change_latency_us = 17.0,
    121	.writeback_dram_clock_change_latency_us = 23.0,
    122	.return_bus_width_bytes = 64,
    123};