cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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display_rq_dlg_helpers.c (17511B)


      1/*
      2 * Copyright 2017 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#include "display_rq_dlg_helpers.h"
     27#include "dml_logger.h"
     28
     29void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_params_st *rq_param)
     30{
     31	dml_print("DML_RQ_DLG_CALC: ***************************\n");
     32	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n");
     33	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
     34	print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_l);
     35	dml_print("DML_RQ_DLG_CALC:  <CHROMA> ===\n");
     36	print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_c);
     37
     38	dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
     39	print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_l);
     40	dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
     41	print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_c);
     42
     43	dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
     44	print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_l);
     45	dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
     46	print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_c);
     47	dml_print("DML_RQ_DLG_CALC: ***************************\n");
     48}
     49
     50void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing)
     51{
     52	dml_print("DML_RQ_DLG_CALC: =====================================\n");
     53	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
     54	dml_print("DML_RQ_DLG_CALC:    chunk_bytes           = %0d\n", rq_sizing->chunk_bytes);
     55	dml_print("DML_RQ_DLG_CALC:    min_chunk_bytes       = %0d\n", rq_sizing->min_chunk_bytes);
     56	dml_print("DML_RQ_DLG_CALC:    meta_chunk_bytes      = %0d\n", rq_sizing->meta_chunk_bytes);
     57	dml_print(
     58			"DML_RQ_DLG_CALC:    min_meta_chunk_bytes  = %0d\n",
     59			rq_sizing->min_meta_chunk_bytes);
     60	dml_print("DML_RQ_DLG_CALC:    mpte_group_bytes      = %0d\n", rq_sizing->mpte_group_bytes);
     61	dml_print("DML_RQ_DLG_CALC:    dpte_group_bytes      = %0d\n", rq_sizing->dpte_group_bytes);
     62	dml_print("DML_RQ_DLG_CALC: =====================================\n");
     63}
     64
     65void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param)
     66{
     67	dml_print("DML_RQ_DLG_CALC: =====================================\n");
     68	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
     69	dml_print(
     70			"DML_RQ_DLG_CALC:    swath_width_ub              = %0d\n",
     71			rq_dlg_param->swath_width_ub);
     72	dml_print(
     73			"DML_RQ_DLG_CALC:    swath_height                = %0d\n",
     74			rq_dlg_param->swath_height);
     75	dml_print(
     76			"DML_RQ_DLG_CALC:    req_per_swath_ub            = %0d\n",
     77			rq_dlg_param->req_per_swath_ub);
     78	dml_print(
     79			"DML_RQ_DLG_CALC:    meta_pte_bytes_per_frame_ub = %0d\n",
     80			rq_dlg_param->meta_pte_bytes_per_frame_ub);
     81	dml_print(
     82			"DML_RQ_DLG_CALC:    dpte_req_per_row_ub         = %0d\n",
     83			rq_dlg_param->dpte_req_per_row_ub);
     84	dml_print(
     85			"DML_RQ_DLG_CALC:    dpte_groups_per_row_ub      = %0d\n",
     86			rq_dlg_param->dpte_groups_per_row_ub);
     87	dml_print(
     88			"DML_RQ_DLG_CALC:    dpte_row_height             = %0d\n",
     89			rq_dlg_param->dpte_row_height);
     90	dml_print(
     91			"DML_RQ_DLG_CALC:    dpte_bytes_per_row_ub       = %0d\n",
     92			rq_dlg_param->dpte_bytes_per_row_ub);
     93	dml_print(
     94			"DML_RQ_DLG_CALC:    meta_chunks_per_row_ub      = %0d\n",
     95			rq_dlg_param->meta_chunks_per_row_ub);
     96	dml_print(
     97			"DML_RQ_DLG_CALC:    meta_req_per_row_ub         = %0d\n",
     98			rq_dlg_param->meta_req_per_row_ub);
     99	dml_print(
    100			"DML_RQ_DLG_CALC:    meta_row_height             = %0d\n",
    101			rq_dlg_param->meta_row_height);
    102	dml_print(
    103			"DML_RQ_DLG_CALC:    meta_bytes_per_row_ub       = %0d\n",
    104			rq_dlg_param->meta_bytes_per_row_ub);
    105	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    106}
    107
    108void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param)
    109{
    110	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    111	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
    112	dml_print(
    113			"DML_RQ_DLG_CALC:     full_swath_bytes   = %0d\n",
    114			rq_misc_param->full_swath_bytes);
    115	dml_print(
    116			"DML_RQ_DLG_CALC:     stored_swath_bytes = %0d\n",
    117			rq_misc_param->stored_swath_bytes);
    118	dml_print("DML_RQ_DLG_CALC:     blk256_width       = %0d\n", rq_misc_param->blk256_width);
    119	dml_print("DML_RQ_DLG_CALC:     blk256_height      = %0d\n", rq_misc_param->blk256_height);
    120	dml_print("DML_RQ_DLG_CALC:     req_width          = %0d\n", rq_misc_param->req_width);
    121	dml_print("DML_RQ_DLG_CALC:     req_height         = %0d\n", rq_misc_param->req_height);
    122	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    123}
    124
    125void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param)
    126{
    127	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    128	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
    129	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
    130	print__data_rq_dlg_params_st(mode_lib, &rq_dlg_param->rq_l);
    131	dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
    132	print__data_rq_dlg_params_st(mode_lib, &rq_dlg_param->rq_c);
    133	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    134}
    135
    136void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param)
    137{
    138	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    139	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
    140	dml_print("DML_RQ_DLG_CALC:    t_mclk_wm_us         = %3.2f\n", dlg_sys_param->t_mclk_wm_us);
    141	dml_print("DML_RQ_DLG_CALC:    t_urg_wm_us          = %3.2f\n", dlg_sys_param->t_urg_wm_us);
    142	dml_print("DML_RQ_DLG_CALC:    t_sr_wm_us           = %3.2f\n", dlg_sys_param->t_sr_wm_us);
    143	dml_print("DML_RQ_DLG_CALC:    t_extra_us           = %3.2f\n", dlg_sys_param->t_extra_us);
    144	dml_print(
    145			"DML_RQ_DLG_CALC:    deepsleep_dcfclk_mhz = %3.2f\n",
    146			dlg_sys_param->deepsleep_dcfclk_mhz);
    147	dml_print(
    148			"DML_RQ_DLG_CALC:    total_flip_bw        = %3.2f\n",
    149			dlg_sys_param->total_flip_bw);
    150	dml_print(
    151			"DML_RQ_DLG_CALC:    total_flip_bytes     = %i\n",
    152			dlg_sys_param->total_flip_bytes);
    153	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    154}
    155
    156void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs)
    157{
    158	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    159	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
    160	dml_print("DML_RQ_DLG_CALC:    chunk_size              = 0x%0x\n", rq_regs->chunk_size);
    161	dml_print("DML_RQ_DLG_CALC:    min_chunk_size          = 0x%0x\n", rq_regs->min_chunk_size);
    162	dml_print("DML_RQ_DLG_CALC:    meta_chunk_size         = 0x%0x\n", rq_regs->meta_chunk_size);
    163	dml_print(
    164			"DML_RQ_DLG_CALC:    min_meta_chunk_size     = 0x%0x\n",
    165			rq_regs->min_meta_chunk_size);
    166	dml_print("DML_RQ_DLG_CALC:    dpte_group_size         = 0x%0x\n", rq_regs->dpte_group_size);
    167	dml_print("DML_RQ_DLG_CALC:    mpte_group_size         = 0x%0x\n", rq_regs->mpte_group_size);
    168	dml_print("DML_RQ_DLG_CALC:    swath_height            = 0x%0x\n", rq_regs->swath_height);
    169	dml_print(
    170			"DML_RQ_DLG_CALC:    pte_row_height_linear   = 0x%0x\n",
    171			rq_regs->pte_row_height_linear);
    172	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    173}
    174
    175void print__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs)
    176{
    177	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    178	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n");
    179	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
    180	print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l);
    181	dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
    182	print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_c);
    183	dml_print("DML_RQ_DLG_CALC:    drq_expansion_mode  = 0x%0x\n", rq_regs->drq_expansion_mode);
    184	dml_print("DML_RQ_DLG_CALC:    prq_expansion_mode  = 0x%0x\n", rq_regs->prq_expansion_mode);
    185	dml_print("DML_RQ_DLG_CALC:    mrq_expansion_mode  = 0x%0x\n", rq_regs->mrq_expansion_mode);
    186	dml_print("DML_RQ_DLG_CALC:    crq_expansion_mode  = 0x%0x\n", rq_regs->crq_expansion_mode);
    187	dml_print("DML_RQ_DLG_CALC:    plane1_base_address = 0x%0x\n", rq_regs->plane1_base_address);
    188	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    189}
    190
    191void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs)
    192{
    193	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    194	dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
    195	dml_print(
    196			"DML_RQ_DLG_CALC:    refcyc_h_blank_end              = 0x%0x\n",
    197			dlg_regs->refcyc_h_blank_end);
    198	dml_print(
    199			"DML_RQ_DLG_CALC:    dlg_vblank_end                  = 0x%0x\n",
    200			dlg_regs->dlg_vblank_end);
    201	dml_print(
    202			"DML_RQ_DLG_CALC:    min_dst_y_next_start            = 0x%0x\n",
    203			dlg_regs->min_dst_y_next_start);
    204	dml_print(
    205			"DML_RQ_DLG_CALC:    refcyc_per_htotal               = 0x%0x\n",
    206			dlg_regs->refcyc_per_htotal);
    207	dml_print(
    208			"DML_RQ_DLG_CALC:    refcyc_x_after_scaler           = 0x%0x\n",
    209			dlg_regs->refcyc_x_after_scaler);
    210	dml_print(
    211			"DML_RQ_DLG_CALC:    dst_y_after_scaler              = 0x%0x\n",
    212			dlg_regs->dst_y_after_scaler);
    213	dml_print(
    214			"DML_RQ_DLG_CALC:    dst_y_prefetch                  = 0x%0x\n",
    215			dlg_regs->dst_y_prefetch);
    216	dml_print(
    217			"DML_RQ_DLG_CALC:    dst_y_per_vm_vblank             = 0x%0x\n",
    218			dlg_regs->dst_y_per_vm_vblank);
    219	dml_print(
    220			"DML_RQ_DLG_CALC:    dst_y_per_row_vblank            = 0x%0x\n",
    221			dlg_regs->dst_y_per_row_vblank);
    222	dml_print(
    223			"DML_RQ_DLG_CALC:    dst_y_per_vm_flip               = 0x%0x\n",
    224			dlg_regs->dst_y_per_vm_flip);
    225	dml_print(
    226			"DML_RQ_DLG_CALC:    dst_y_per_row_flip              = 0x%0x\n",
    227			dlg_regs->dst_y_per_row_flip);
    228	dml_print(
    229			"DML_RQ_DLG_CALC:    ref_freq_to_pix_freq            = 0x%0x\n",
    230			dlg_regs->ref_freq_to_pix_freq);
    231	dml_print(
    232			"DML_RQ_DLG_CALC:    vratio_prefetch                 = 0x%0x\n",
    233			dlg_regs->vratio_prefetch);
    234	dml_print(
    235			"DML_RQ_DLG_CALC:    vratio_prefetch_c               = 0x%0x\n",
    236			dlg_regs->vratio_prefetch_c);
    237	dml_print(
    238			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_l   = 0x%0x\n",
    239			dlg_regs->refcyc_per_pte_group_vblank_l);
    240	dml_print(
    241			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_c   = 0x%0x\n",
    242			dlg_regs->refcyc_per_pte_group_vblank_c);
    243	dml_print(
    244			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_l  = 0x%0x\n",
    245			dlg_regs->refcyc_per_meta_chunk_vblank_l);
    246	dml_print(
    247			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_c  = 0x%0x\n",
    248			dlg_regs->refcyc_per_meta_chunk_vblank_c);
    249	dml_print(
    250			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_l     = 0x%0x\n",
    251			dlg_regs->refcyc_per_pte_group_flip_l);
    252	dml_print(
    253			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_c     = 0x%0x\n",
    254			dlg_regs->refcyc_per_pte_group_flip_c);
    255	dml_print(
    256			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_l    = 0x%0x\n",
    257			dlg_regs->refcyc_per_meta_chunk_flip_l);
    258	dml_print(
    259			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_c    = 0x%0x\n",
    260			dlg_regs->refcyc_per_meta_chunk_flip_c);
    261	dml_print(
    262			"DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_l         = 0x%0x\n",
    263			dlg_regs->dst_y_per_pte_row_nom_l);
    264	dml_print(
    265			"DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_c         = 0x%0x\n",
    266			dlg_regs->dst_y_per_pte_row_nom_c);
    267	dml_print(
    268			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_l      = 0x%0x\n",
    269			dlg_regs->refcyc_per_pte_group_nom_l);
    270	dml_print(
    271			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_c      = 0x%0x\n",
    272			dlg_regs->refcyc_per_pte_group_nom_c);
    273	dml_print(
    274			"DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_l        = 0x%0x\n",
    275			dlg_regs->dst_y_per_meta_row_nom_l);
    276	dml_print(
    277			"DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_c        = 0x%0x\n",
    278			dlg_regs->dst_y_per_meta_row_nom_c);
    279	dml_print(
    280			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_l     = 0x%0x\n",
    281			dlg_regs->refcyc_per_meta_chunk_nom_l);
    282	dml_print(
    283			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_c     = 0x%0x\n",
    284			dlg_regs->refcyc_per_meta_chunk_nom_c);
    285	dml_print(
    286			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_l  = 0x%0x\n",
    287			dlg_regs->refcyc_per_line_delivery_pre_l);
    288	dml_print(
    289			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_c  = 0x%0x\n",
    290			dlg_regs->refcyc_per_line_delivery_pre_c);
    291	dml_print(
    292			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_l      = 0x%0x\n",
    293			dlg_regs->refcyc_per_line_delivery_l);
    294	dml_print(
    295			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_c      = 0x%0x\n",
    296			dlg_regs->refcyc_per_line_delivery_c);
    297	dml_print(
    298			"DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur0           = 0x%0x\n",
    299			dlg_regs->chunk_hdl_adjust_cur0);
    300	dml_print(
    301			"DML_RQ_DLG_CALC:    dst_y_offset_cur1               = 0x%0x\n",
    302			dlg_regs->dst_y_offset_cur1);
    303	dml_print(
    304			"DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur1           = 0x%0x\n",
    305			dlg_regs->chunk_hdl_adjust_cur1);
    306	dml_print(
    307			"DML_RQ_DLG_CALC:    vready_after_vcount0            = 0x%0x\n",
    308			dlg_regs->vready_after_vcount0);
    309	dml_print(
    310			"DML_RQ_DLG_CALC:    dst_y_delta_drq_limit           = 0x%0x\n",
    311			dlg_regs->dst_y_delta_drq_limit);
    312	dml_print(
    313			"DML_RQ_DLG_CALC:    xfc_reg_transfer_delay          = 0x%0x\n",
    314			dlg_regs->xfc_reg_transfer_delay);
    315	dml_print(
    316			"DML_RQ_DLG_CALC:    xfc_reg_precharge_delay         = 0x%0x\n",
    317			dlg_regs->xfc_reg_precharge_delay);
    318	dml_print(
    319			"DML_RQ_DLG_CALC:    xfc_reg_remote_surface_flip_latency = 0x%0x\n",
    320			dlg_regs->xfc_reg_remote_surface_flip_latency);
    321	dml_print(
    322			"DML_RQ_DLG_CALC:    refcyc_per_vm_dmdata            = 0x%0x\n",
    323			dlg_regs->refcyc_per_vm_dmdata);
    324
    325	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    326}
    327
    328void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs)
    329{
    330	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    331	dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
    332	dml_print(
    333			"DML_RQ_DLG_CALC:    qos_level_low_wm                  = 0x%0x\n",
    334			ttu_regs->qos_level_low_wm);
    335	dml_print(
    336			"DML_RQ_DLG_CALC:    qos_level_high_wm                 = 0x%0x\n",
    337			ttu_regs->qos_level_high_wm);
    338	dml_print(
    339			"DML_RQ_DLG_CALC:    min_ttu_vblank                    = 0x%0x\n",
    340			ttu_regs->min_ttu_vblank);
    341	dml_print(
    342			"DML_RQ_DLG_CALC:    qos_level_flip                    = 0x%0x\n",
    343			ttu_regs->qos_level_flip);
    344	dml_print(
    345			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_l     = 0x%0x\n",
    346			ttu_regs->refcyc_per_req_delivery_pre_l);
    347	dml_print(
    348			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_l         = 0x%0x\n",
    349			ttu_regs->refcyc_per_req_delivery_l);
    350	dml_print(
    351			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_c     = 0x%0x\n",
    352			ttu_regs->refcyc_per_req_delivery_pre_c);
    353	dml_print(
    354			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_c         = 0x%0x\n",
    355			ttu_regs->refcyc_per_req_delivery_c);
    356	dml_print(
    357			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur0      = 0x%0x\n",
    358			ttu_regs->refcyc_per_req_delivery_cur0);
    359	dml_print(
    360			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur0  = 0x%0x\n",
    361			ttu_regs->refcyc_per_req_delivery_pre_cur0);
    362	dml_print(
    363			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur1      = 0x%0x\n",
    364			ttu_regs->refcyc_per_req_delivery_cur1);
    365	dml_print(
    366			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur1  = 0x%0x\n",
    367			ttu_regs->refcyc_per_req_delivery_pre_cur1);
    368	dml_print(
    369			"DML_RQ_DLG_CALC:    qos_level_fixed_l                 = 0x%0x\n",
    370			ttu_regs->qos_level_fixed_l);
    371	dml_print(
    372			"DML_RQ_DLG_CALC:    qos_ramp_disable_l                = 0x%0x\n",
    373			ttu_regs->qos_ramp_disable_l);
    374	dml_print(
    375			"DML_RQ_DLG_CALC:    qos_level_fixed_c                 = 0x%0x\n",
    376			ttu_regs->qos_level_fixed_c);
    377	dml_print(
    378			"DML_RQ_DLG_CALC:    qos_ramp_disable_c                = 0x%0x\n",
    379			ttu_regs->qos_ramp_disable_c);
    380	dml_print(
    381			"DML_RQ_DLG_CALC:    qos_level_fixed_cur0              = 0x%0x\n",
    382			ttu_regs->qos_level_fixed_cur0);
    383	dml_print(
    384			"DML_RQ_DLG_CALC:    qos_ramp_disable_cur0             = 0x%0x\n",
    385			ttu_regs->qos_ramp_disable_cur0);
    386	dml_print(
    387			"DML_RQ_DLG_CALC:    qos_level_fixed_cur1              = 0x%0x\n",
    388			ttu_regs->qos_level_fixed_cur1);
    389	dml_print(
    390			"DML_RQ_DLG_CALC:    qos_ramp_disable_cur1             = 0x%0x\n",
    391			ttu_regs->qos_ramp_disable_cur1);
    392	dml_print("DML_RQ_DLG_CALC: =====================================\n");
    393}